Reconfigurable vector-FFT/IFFT, vector-multiplier/divider
View Patent ↗Systems and methods are described for providing a reconfigurable circuit having multiple distinct circuit configurations with respective distinct operating modes The circuit may be controllably configures to perform a fast Fourier transform function, a multiplier function, and a divider function. In one exemplary practical application of the invention, the fast Fourier transform function, multiplier function, and divider function may be used for signal demodulation, channel equalization and channel estimation for a WLAN IEEE 802.11 system.
1. A reconfigurable mathematical operation circuit, comprising:
a coordinate rotation digital computer (CORDIC) circuit having a plurality of reconfigurable components for perfonning a respective plurality of distinct mathematical functions; and
a controller for controlling a configuration of said CORDIC circuit, whereby, in a first configuration said CORDIC circuit performs a fast Fourier transform function, in a second configuration said CORDIC circuit performs a multiplier function, and in a third configuration said CORDIC circuit performs a divider function.
2. The reconfigurable mathematical operation circuit of claim 1 ,said first configuration including a radix-N fast Fourier transform circuit and a plurality of registers configured to perform iteratively a fast Fourier transform function.
3. The reconfigurable mathematical operation circuit of claim 2 , said first configuration including a radix-4 fast Fourier transform circuit.
4. The reconfigurable mathematical operation circuit of claim 1 , said second configuration including a vector multiplier circuit configured to perform a vector multiplication function.
5. The reconfigurable mathematical operation circuit of claim 1 , said third configuration including a vector divider circuit configured to perform a vector division function.
6. A reconfigurable WLAN IEEE 802.11 receiver circuit, comprising:
reconfigurable circuitry including CORDIC circuit components configurable to form a fast Fourier transform WLAN signal demodulation circuit, a multiplier-based WLAN channel equalization circuit, and a divider-based WLAN channel estimation circuit; and
a controller for controlling a configuration of said circuit components to form a WLAN IEEE 802.11 receiver.
7. The reconfigurable WLAN IEEE 802.11 receiver circuit of claim 6 , said fast Fourier transform WLAN signal demodulation circuit including a plurality of registers connected to the output of a plurality of radix-4 FFT stages.
8. The reconfigurable WLAN IEEE 802.11 receiver circuit of claim 7 , each of said plurality of radix-4 FFT stages comprising two radix-2 FFT stages.
9. A method of operating a reconfigurable circuit to condition a WLAN signal, comprising:
providing a CORDIC circuit comprising a reconfigurable circuit having multiple distinct circuit configurations with respective distinct operating modes;
configuring said reconfigurable circuit in a first configuration to perform a fast Fourier transform function;
configuring said reconfigurable circuit in a second configuration to perform a multiplier function; and
configuring said reconfigurable circuit in a third configuration to perform a divider function.
10. The method of operating a reconfigurable circuit to condition a WLAN signal of claim 9 , said fast Fourier transform function demodulating said WLAN signal.
11. A method of operating a reconfigurable circuit to condition a WLAN signal of claim 9 , said multiplier function equalizing a channel of said WLAN signal.
12. A method of operating a reconfigurable circuit to condition a WLAN signal of claim 9 , said divider function estimating a channel of said WLAN signal.
13. A method of operating a reconfigurable circuit to condition a WLAN signal of claim 9 , said fast Fourier transform function comprising, iteratively determining a fast Fourier transform of said WLAN signal.