Granted Patent B2

US 7,323,373 · App. 11/339,133 · Granted Jan 29, 2008

Abstract

Claims (32)

1. A method of forming a semiconductor device, the method comprising:

patterning a semiconductor layer of silicon to form a vertical active region and a horizontal active region, wherein the horizontal active region is adjacent the vertical active region and the semiconductor layer overlies an insulating layer;

forming a spacer adjacent the vertical active region and over a portion of the horizontal active region;

forming a mask layer over the vertical active region;

implanting oxygen into the horizontal active region, the horizontal active region chemically remaining silicon

removing the spacer and the mask layer with a chemical etchant that removes the spacer and mask layer without removing the horizontal active region or the vertical active region;

forming a gate dielectric over the vertical active region after removing the spacer;

forming a gate electrode over the gate dielectric and a portion of the horizontal active region; and

annealing the oxygen after removing the spacer to make the horizontal active region chemically change from silicon to an insulating oxide material to electrically insulate the gate electrode,

wherein the insulating oxide material electrically insulates the gate electrode from the insulating layer, which is a buried oxide layer, and the vertical active region is in direct contact with the buried oxide layer.

2. A method of forming a semiconductor device, the method comprising:

providing a semiconductor substrate comprising a buried oxide layer;

forming a vertical active region and a horizontal active region over the buried oxide layer wherein:

the vertical active region comprises a source region, a channel region, and a drain region and has a sidewall;

the channel region has a first dimension, wherein the first dimension is perpendicular to the sidewall;

the source region has a second dimension, wherein the second dimension is perpendicular to the sidewall and is greater than the first dimension; and

the drain region has a third dimension, wherein the third dimension is perpendicular to the sidewall and is greater than the first dimension;

prior to forming a source, a channel and a drain respectively within the source region, the channel region and the drain region, oxidizing all of the sidewall of the vertical active region by consuming a portion of the channel region and oxidizing less than all of the horizontal active region to form an oxide region along all of the sidewall, the channel region having a resulting fourth dimension that is less than the first dimension;

removing the oxide region with a chemical etch wherein a remainder of the horizontal active region protects the buried oxide layer from the chemical etch;

forming a gate dielectric over the vertical active region; and

forming a gate electrode over the gate dielectric.

3. A method of forming a transistor, the method comprising:

providing an insulating layer;

forming a semiconductor layer of silicon overlying the insulating layer and patterning the semiconductor layer to form a vertical fin and an adjacent horizontal region;

forming an etch stop liner on the vertical fin and the adjacent horizontal region;

forming a mask layer over the vertical fin;

forming a sidewall spacer adjacent sidewalls of the vertical fin;

implanting oxygen into the adjacent horizontal region;

removing the sidewall spacer with a chemical etchant that does not chemically react with the adjacent horizontal region, thereby not removing the vertical fin and the adjacent horizontal region;

after removing the sidewall spacer, annealing the adjacent horizontal region to activate the oxygen that was implanted and forming an oxide;

forming a drain and a source at opposing ends of the vertical fin; and

forming a gate electrode overlying the vertical fin and between the source and the drain.

Assignments (22)