Layout modification using multilayer-based constraints
View Patent ↗A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.
1. A method for improving manufacturability of a semiconductor device layout design comprising:
performing at least one interlayer space check and one intralayer space check on more than one of multiple interacting layers of a target design; and
modifying the target design to create an altered target design database in response to the results of the space checks, wherein modifying the target design includes a first movement of a group of at least one edge on a feature within the target design to decrease a risk of one of feature widths, feature enclosure and feature spaces being patterned smaller than designed, and wherein modifying the target design further includes a second movement of a group of at least one edge on a feature to decrease a risk of one of feature widths, feature enclosure and feature spaces being patterned smaller than designed in response to the first movement of edges, wherein the first movement includes moving predetermined feature edges by moving edges of routing poly outward and interacting routing poly inward.
2. The method of claim 1 , wherein modifying the target design includes utilizing at least one of design rule checking (DRC), rule-based optical proximity correction (RB-OPC) and model-based optical proximity correction (MB-OPC) software functions to perform one or more of the first movement and the second movement.
3. The method of claim 1 , wherein the first movement includes moving predetermined feature edges by use of prioritization of the feature edges to be moved based upon at least one of electrical yield information and patterning process control capability.
4. The method of claim 1 , wherein the first movement includes moving predetermined feature edges by shifting edges of vias and shifting edges of interacting metal features.
5. The method of claim 1 , wherein the first movement includes moving predetermined feature edges by optimization of the distance which feature edges are moved based upon mask error factor (MEF) information.
6. The method of claim 1 , wherein the first movement includes moving predetermined feature edges by shifting an edge of an interconnect feature with space less than a predetermined value to another non-electrically connected interconnect feature on the same layer in order to decrease the risk of feature merging and without reducing interconnect enclosure of via or contact features.
7. The method of claim 6 , wherein shifting nearby edges of non-electrically connected interconnect features away from the other feature includes the shifting of via or contact features to prevent reduction in the interconnect enclosure of via or contact features.
8. The method of claim 1 , wherein the first movement further includes moving predetermined feature edges by the shifting of at least one edge creating a concave corner from at least one of poly and active layers in response to the concave corner being at a space to the overlap of poly and active layers less than a predetermined value.
9. The method of claim 1 , wherein modifying the target design further includes utilizing at least one of design rule checking (DRC) and layout versus schematic (LVS) software functions to verify that the design modifications have not violated predetermined design rules or circuit functionality.
10. The method of claim 9 , wherein verification that the design modifications have not violated predetermined design rules or circuit functionality further includes removing the design modifications in response to a detection of violations.
11. The method of claim 1 , wherein the first movement includes moving predetermined feature edges by upsizing features to be larger in a wafer circuit pattern than the corresponding features as drawn in a design database.
12. A method for improving manufacturability of a semiconductor device layout design comprising:
performing at least one interlayer space check and one intralayer space check on more than one of multiple interacting layers of a target design; and
modifying the target design to create an altered target design database in response to the results of the space checks, wherein modifying the target design includes a first movement of a group of at least one edge on a feature within the target design to decrease a risk of one of feature widths, feature enclosure and feature spaces being patterned smaller than designed, and wherein modifying the target design further includes a second movement of a group of at least one edge on a feature to decrease a risk of one of feature widths, feature enclosure and feature spaces being patterned smaller than designed in response to the first movement of edges, wherein the first movement includes moving predetermined feature edges by moving an edge of a line-end outward and moving an edge of an interacting feature inward.
13. A method for improving manufacturability of a semiconductor device layout design comprising:
performing at least one interlayer space check and one intralayer space check on more than one of multiple interacting layers of a design; and
modifying at least one of a contact, via or implant target design layers of the target design in response to results of the at least one of the space checks to create an altered target design database, wherein modifying the design includes moving at least one or more predetermined edges of a feature on the at least one of the contact, via or implant target design layers in order to decrease a risk of at least one of feature widths, feature spaces, feature electrical conductivity and feature enclosures being manufactured smaller than designed, wherein moving predetermined feature edges includes determining if the interconnect area enclosing a predetermined number of vias is greater than a predetermined value and upsizing the via to reduce the risk of the via conductivity being manufactured less than a predetermined value.
14. The method of claim 13 , wherein modifying the target design includes utilizing at least one of design rule checking (DRC), rule-based optical proximity correction (RB-OPC) and model-based optical proximity correction (MB-OPC) software functions in order to move edges.
15. The method of claim 13 , wherein shifting at least one edge of a via causes at least one of the position of the center of the via to be shifted and the shape of the via in the design database to become non-square.
16. The method of claim 13 , wherein shifting at least one edge of a via includes at least partially merging at least two electrically connected vias.
17. The method of claim 13 , wherein moving predetermined feature edges further includes the expanding of at least one edge outwards greater than one time and performing a subtraction operation between the expanded edges to create a sub-resolution assist feature.
18. The method of claim 17 , wherein the sub-resolution assist feature is created to reduce the amount of obliquely reflected light incident from a reflective substrate upon a photoresist feature during a photolithography process.
19. The method of claim 13 , wherein moving predetermined feature edges further includes optimization of the distance at which feature edges are moved based upon mask error factor (MEF) information.
20. The method of claim 13 , wherein modifying the design further includes the use of at least one of design rule checking (DRC) and layout versus schematic (LVS) software functions to verify that the design modifications have not violated predetermined design rules or circuit functionality.
21. The method of claim 13 , wherein modifying the design further includes shifting an edge of an implant feature to reduce the risk of dopant interdiffusion between opposite polarity implant regions.
22. The method of claim 13 , wherein moving predetermined feature edges includes upsizing features to be larger in a wafer circuit pattern than the corresponding features as drawn in the design database.