Granted Patent B2

US 7,670,895 · App. 11/409,633 · Granted Mar 2, 2010

Abstract

Claims (70)

1. A process of forming an electronic device comprising:

providing a workpiece including a substrate, an insulating layer, and a semiconductor layer, wherein the insulating layer lies between the substrate and the semiconductor layer;

patterning the semiconductor layer to define an opening extending to an insulating layer, wherein after patterning the semiconductor layer:

the opening has a bottom, wherein the insulating layer lies along the bottom of the opening;

the semiconductor layer has a sidewall and a surface;

the surface is spaced apart from the insulating layer; and

the sidewall extends from the surface towards the insulating layer;

forming a first layer over the substrate, wherein the first layer substantially fills the opening within the semiconductor layer;

removing a part of the first layer from within the opening, wherein after removing the part of the first layer:

a remaining portion of the first layer lies within the opening and adjacent to the sidewall and lies along substantially all of the bottom of the trench;

the remaining portion of the first layer is spaced apart from the surface;

the remaining portion of the first layer has a first thickness at a center of the opening and a second thickness at a point closest to the sidewall, wherein as measured from the bottom of the opening, the first thickness is at least as thick as the second thickness:

the remaining portion of the first layer fills approximately 20% to approximately 50% of the opening: and

a portion of the sidewall is exposed within the opening;

oxidizing the semiconductor layer while the remaining portion of the first layer lies within the opening, wherein:

a first corner of the semiconductor layer immediately adjacent to the surface becomes rounded during oxidizing the semiconductor layer;

a second corner of the semiconductor layer at an interface between the semiconductor layer and the insulating layer substantially maintains its shape during oxidizing the semiconductor layer; and

the portion of the sidewall of the semiconductor layer is oxidized;

depositing an insulating layer that substantially completely fills a rest of the opening after oxidizing the semiconductor layer; and

removing a portion of the insulating layer lying outside the opening to form a field isolation region.

2. The process of claim 1 , further comprising:

forming a gate dielectric layer adjacent to the surface and the first corner of the semiconductor layer, wherein forming the gate dielectric layer is performed after oxidizing the semiconductor layer; and

forming a gate electrode, wherein:

the gate dielectric layer lies between the semiconductor layer and the gate electrode; and

the gate electrode extends over the field isolation region and lies adjacent to the surface and the first corner of the semiconductor layer.

3. The process of claim 2 , wherein after forming the gate electrode, the field isolation region substantially fills the opening in the semiconductor layer.

4. The process of claim 1 , wherein forming the first layer comprises depositing the first layer using a PECVD technique.

5. The process of claim 1 , wherein forming the first layer comprises depositing the first layer using an inductively coupled plasma.

6. The process of claim 1 , wherein removing the part of the first layer comprises etching the first layer using a substantially isotropic etchant.

7. The process of claim 1 , wherein removing the part of the first layer is performed using a wet chemical etchant.

8. The process of claim 7 , wherein:

forming the first layer comprises depositing a nitride layer; and

removing the part of the first layer comprises exposing the nitride layer to H 3 PO 4 .

9. The process of claim 7 , wherein removing the part of the first layer comprises removing the part of the first layer, wherein, as seen from a cross-sectional view, the remaining portion has a dome shape.

10. The process of claim 1 , wherein the remaining portion has a substantially uniform thickness, as measured from the bottom of the opening.

11. The process of claim 1 , wherein:

depositing the insulating layer comprises depositing an oxide layer; and

removing the portion of the insulating layer comprises polishing the oxide layer.

12. The process of claim 1 , wherein removing the portion of the insulating layer comprises polishing the insulating layer.

13. The process of claim 1 , wherein providing a workpiece comprises providing a workpiece including the semiconductor layer, wherein the semiconductor layer comprises germanium.

14. A process of forming an electronic device comprising:

patterning a semiconductor layer to define an opening extending to an insulating layer underlying the semiconductor layer, wherein the insulating layer between a substrate and the semiconductor layer, and after patterning the semiconductor layer:

the opening has a bottom;

the semiconductor layer includes a sidewall, a surface, a first corner, and a second corner;

the surface is spaced apart from the bottom of the opening;

the first corner is adjacent to the surface;

the second corner is adjacent to the insulating layer; and

the sidewall extends from the first corner to the second corner;

forming a first layer over the semiconductor layer and within the opening;

removing a part of the first layer from within the opening, wherein after removing the part of the first layer:

a remaining portion of the first layer lies within the opening and adjacent to the bottom and the sidewall;

the remaining portion of the first layer is spaced apart from the surface; and

as seen from a cross-sectional view, the remaining portion has a dome shape;

oxidizing the semiconductor layer, wherein:

the first corner becomes rounded during oxidizing the semiconductor layer; and

the second corner substantially maintains its shape during oxidizing the semiconductor layer;

depositing an oxide layer that substantially completely fills a rest of the opening;

polishing the oxide layer to remove a portion of the oxide layer lying outside the opening;

forming a gate dielectric layer adjacent to the surface and the first corner of the semiconductor layer; and

forming a gate electrode, wherein:

the gate dielectric layer lies between the semiconductor layer and the gate electrode; and

the gate electrode lies adjacent to the surface and the first corner of the semiconductor layer.

15. The process of claim 14 , wherein polishing the oxide layer forms a field isolation region within the opening in the semiconductor layer.

16. The process of claim 15 , wherein forming the gate electrode is performed such that the gate electrode extends over the field isolation region that substantially fills the opening in the semiconductor layer.

17. The process of claim 16 , wherein:

patterning the semiconductor layer comprises patterning the semiconductor layer to define the opening having a depth; and

removing the part of the first layer comprises removing the part of the first layer, wherein the remaining portion of the first layer has a thickness at a center of the opening that is in a range of approximately 20% to approximately 50% of the depth of the opening.

18. The process of claim 16 , wherein forming the first layer comprises depositing the first layer using an inductively coupled plasma.

19. The process of claim 16 , wherein removing the part of the first layer comprises etching the first layer using a substantially isotropic etchant.

20. The process of claim 16 , wherein removing the part of the first layer is performed using a wet chemical etchant.

Assignments (39)