IP Library Granted Patent US 8,041,132
Granted Patent B2
US 8,041,132 · App. 12/147,850 · Granted Oct 18, 2011

System and method for load balancing a video signal in a multi-core processor

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,041,132
App. No.
12/147,850
Granted
Oct 18, 2011
Kind
B2
Abstract

Sequential video data frames are encoded using cores including a first core and a second core. A first beginning frame is divided into slices. The first core is assigned to process a first slice. The second core is assigned to process a second slice. The first beginning frame is processed using the cores which results in a first ending frame in which the first slice was partitioned into a third slice and a fourth slice. The third slice was processed by the first core. The fourth slice and the second slice were processed by the second core. A second beginning frame, which immediately follows the first ending frame, is divided into a second plurality of slices. The first core is assigned to the third slice. The second core is assigned to a fifth slice which has a size equal to a sum of the second and fourth slices.

Claims (40)

1. A method of encoding sequential video data frames using a plurality of cores comprising a first core and a second core, the method comprising:

dividing a beginning portion of a first frame into a first plurality of slices among the plurality of cores in which the first core is assigned to process a first slice of the plurality of slices and the second core is assigned to process a second slice of the plurality of slices;

processing the first frame using the plurality of cores;

partitioning the first slice into a third slice and a fourth slice, wherein the third slice is processed by the first core and the fourth slice and the second slice are processed by the second core; and

dividing a second frame, which immediately follows the first ending frame, into a second plurality of slices among the plurality of cores in which the first core is assigned to a fifth slice equivalent in size to the third slice and the second core is assigned to a sixth slice which has a size equal to a sum of the second and fourth slices.

2. The method of claim 1 , wherein the plurality of cores comprises a master core and a plurality of slave cores.

3. The method of claim 2 , wherein the step of processing the first frame is further characterized by the master core partitioning the slices according to a protocol.

4. The method of claim 3 , wherein the step of dividing the second frame is further characterized by each of the plurality of cores being assigned to a slice having a plurality of macroblocks equal in number to the number of macroblocks processed on the first frame.

5. The method of claim 1 , further comprising:

processing the second frame using the plurality of cores to produce a modified second frame.

6. The method of claim 5 , wherein the step of processing the second frame is further characterized as partitioning the second plurality of slices into a third plurality of slices greater in number than the second plurality of slices.

7. The method of claim 6 , wherein the step of processing the second frame is further characterized by each slice of the third plurality of slices being processed by one of the plurality of cores, wherein each core processes a slice having a size equal to a sum of the sizes of the slices that it processed at an end of the first frame.

8. The method of claim 1 , wherein the step of dividing the second frame is further characterized by the second plurality of slices being of a number of slices equal to a number of slices of the first plurality of slices.

9. The method of claim 1 , wherein the second slice and the fourth slice are non-adjacent.

10. A method of processing frames, comprising:

providing a processing unit comprising a plurality of cores of a first number;

dividing a first frame into a first plurality of slices of the first number, wherein each slice of the first plurality of slices has a size;

assigning each core of the plurality of cores to a slice of the first plurality of slices, wherein each slice of the first plurality of slices has a core of the plurality of cores assigned to it;

initially processing a beginning portion of the first frame with the plurality of cores processing the first plurality of slices as assigned according to the step of assigning each core of the plurality of cores to a slice of the first plurality of slices;

processing an ending portion of the first frame, wherein the ending portion of the first frame has a second plurality of slices of a second number, wherein the second number is greater than the first number, wherein each core has processed at least one slice of the second plurality of slices and at least one core has processed more than slice of the second plurality of slices, wherein each core has processed an amount of the first ending frame equal to a sum of the slices processed by it;

dividing a beginning portion of a second frame into a third plurality of slices of the first number;

assigning each core of the plurality of cores to a slice of the third plurality of slices, wherein each slice of the third plurality of slices has a core of the plurality of cores assigned to it, wherein each core is assigned to an amount of the frame equal to the amount it processed on the ending portion of the first frame; and

initially processing the beginning portion of the second frame with the plurality of cores processing the third plurality of slices as assigned according to the step of assigning each core of the plurality of cores to a slice of the third plurality of slices.

11. The method of claim 10 , further comprising:

finally processing the second frame to produce a modified second frame.

12. The method of claim 11 , wherein the step of finally processing the second frame is further characterized by an ending portion of the second frame comprising a fourth plurality of slices greater in number than the third plurality of slices.

13. The method of claim 10 , wherein the step of processing an ending portion the first frame is further characterized by a master core of the plurality of cores controlling the plurality of cores according to a protocol.

14. The method of claim 10 , wherein the method operates in compliance with standard H.264.

15. The method of claim 10 , wherein the first frame and the second frame comprise a plurality of macroblocks.

16. The method of claim 15 , wherein a size equal to a sum of the first plurality of slices is equal to a size equal to a sum of the plurality of macroblocks.

17. The method of claim 10 , further comprising initially processing a third frame with the cores processing sizes equal to the sizes processed at the ending portion of the second frame.

18. An encoder, comprising:

a plurality of slave cores, wherein each slave core is configured to process one or more slices of a frame;

a master core that directs operation of the slave cores and is configured to process one or more slices of a frame, wherein:

the master core is configured to assign itself and each slave core to a single slice of a first plurality of slices of a beginning portion of a first frame, wherein a number of slices of the first plurality of slices is equal to a number of slave cores plus one for the master core;

the master core is configured to partition the slices of the first plurality of slices to result in a second plurality of slices greater in number than the first plurality of slices according to a protocol based on relative processing complexity among the first plurality of slices;

the master core is configured to selectively assign itself and each slave core of the plurality of slave cores to process the second plurality of slices at an ending portion of the first frame, wherein a size of slice processed by each core is in accordance with the protocol; and

the master core is configured to assign itself and each slave core to a single slice of a third plurality of slices of a beginning portion of a second frame, wherein a number of slices of the third plurality of slices is equal to a number of slices of the first plurality of slices and less than a number of slices of the second plurality of slices; wherein each slave core is assigned to a slice having a size equal to the size processed by it during the ending portion of the first frame.

19. The encoder of claim 18 , further comprising a memory shared among the master core and the slave cores.

20. The encoder of claim 18 , wherein the beginning portion of the first frame comprises a plurality of macroblocks, wherein a size equal to a sum of the first plurality of slices is equal to a size equal to a sum of the plurality of macroblocks which is equal to a size of a sum of the second plurality of slices.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
323.01(C) ASSIGNMENT OR CHANGE OF NAME IMPROPERLY FILED AND RECORDED BY ANOTHER PERSON AGAINST OWNER'S PATENT Recorded Oct 3, 2019
From: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 052459/0656 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2017
From: NORTH STAR INNOVATIONS INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 041717/0736 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0719 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024085/0001 →
SECURITY AGREEMENT Recorded Sep 24, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021570/0449 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2008
From: YAN, YONG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 021160/0977 →