Method of making a multi-gate device
View Patent ↗A semiconductor device has two types of multi-gate transistors, N channel and P channel, in which each type has a bottom gate and a top gate. The bottom gate and the top gate of the N channel transistors are chosen to be of a metal or metals that are for optimizing the performance of the N channel transistors. Similarly, the bottom gate and the top gate of the P channel transistors are chosen to be of a metal or metals that are for optimizing the performance of the P channel transistors.
1. A method of forming a planar double gate device comprising:
forming a first bottom gate stack on a semiconductor substrate in a first-type transistor region;
forming a second bottom gate stack on the semiconductor substrate in a second-type transistor region;
forming a channel layer from the semiconductor substrate;
forming a first top gate stack on a top dielectric layer surface in one selected from a group consisting of the first-type transistor region and the second-type transistor region;
forming a second top gate stack over the channel layer in the other of the first-type transistor region or second-type transistor region, different from the transistor region of the first top gate stack;
patterning the first top gate stack and the second top gate stack to form a patterned first top gate stack and a patterned second top gate stack in respective ones of the first-type transistor region or the second-type transistor region;
forming initial sidewall spacers on the patterned first top gate stack and on the patterned second top gate stack;
patterning the channel layer (i) in a region corresponding to the region of the patterned first top gate stack, using the patterned first top gate stack with initial sidewall spacers as a mask to leave a patterned first channel layer and (ii) in a region corresponding to a region of the patterned second top gate stack, using the patterned second top gate stack with initial sidewall spacers as a mask to leave a patterned second channel layer;
forming second sidewall spacers on (i) the patterned semiconductor channel layer and the patterned first top gate stack with initial sidewall spacers and (ii) the patterned semiconductor channel layer and the patterned second top gate stack with initial sidewall spacers;
patterning (i) one of (a) a first bottom gate stack or (b) a second bottom gate stack in a region corresponding to the region of the patterned first top gate stack, using the patterned semiconductor channel layer with second sidewall spacers and the patterned first top gate stack with initial sidewall spacers as a mask and (ii) the other one of (a) the first bottom gate stack or (b) the second bottom gate stack in a region corresponding to the region of the patterned second top gate stack, using the patterned semiconductor channel layer with second sidewall spacers and the patterned second top gate stack with initial sidewall spacers as a mask;
defining (i) a first bottom gate dimension in the first bottom gate stack in the first-type transistor region, wherein defining the bottom gate dimension in the first bottom gate stack corresponds to patterning the first bottom gate stack and (ii) a second bottom gate dimension in the second bottom gate stack in the second-type transistor region, wherein defining the second bottom gate dimension in the second bottom gate stack corresponds to patterning the second bottom gate stack;
depositing a dielectric fill material into void regions proximate to the patterned first and second bottom gate stacks and the patterned first and second top gate stacks, wherein the void regions comprise voids created during the patterning of the first and second bottom gate stacks in respective first-type and second-type transistor regions;
forming source/drain cavities in the dielectric fill material within
(i) the first-type transistor region, the source/drain cavities extending along a height dimension of (a) one of the patterned first top gate stack or patterned second top gate stack within the first-type transistor region, (b) the patterned first channel layer, and (c) the patterned first bottom gate stack in the first-type transistor region, the source/drain cavities further exposing sidewall portions of the patterned semiconductor channel layer in the first-type transistor region, and
(ii) the second-type transistor region, the source/drain cavities extending along a height dimension of (a) the other one of the patterned first top gate stack or patterned second top gate stack within the second-type transistor region, (b) the patterned second channel layer, and (c) the patterned second bottom gate stack in the second-type transistor region, the source/drain cavities further exposing sidewall portions of the patterned semiconductor channel layer in the second-type transistor region; and
filling the source/drain cavities within (i) the first-type transistor region with a first source/drain material and (ii) the second-type transistor region with a second source/drain material.
2. The method of claim 1 , wherein the first bottom gate stack comprises a first bottom gate dielectric, a first bottom gate conductor, and a cap layer.
3. The method of claim 2 , wherein the second bottom gate stack comprises a second bottom gate dielectric, a second bottom gate conductor, and a cap layer, the second bottom gate conductor being different from the first bottom gate conductor.
4. The method of claim 3 , wherein the first bottom gate stack further comprises the second bottom gate conductor disposed between the first bottom gate conductor and the cap layer.
5. The method of claim 3 , further wherein the first bottom gate dielectric and the second bottom gate dielectric comprise the same bottom gate dielectric, and wherein the cap layer of the first bottom gate stack and of the second bottom gate stack comprise the same cap layer.
6. The method of claim 3 , wherein the first bottom gate conductor comprises a first metal having a first work-function and wherein the second bottom gate conductor comprises a second metal having a second work-function.
7. The method of claim 6 , wherein:
the first top gate stack comprises a first top gate dielectric, a first top gate conductor, and a first hard mask layer; and
the first top gate conductor comprises a third metal having a third work-function and wherein the second top gate conductor comprises a fourth metal having a fourth work-function, the fourth work-function being different from the third work-function.
8. The method of claim 3 , wherein the first bottom gate conductor in the first-type transistor region is co-planar with the second bottom gate conductor in the second-type transistor region.
9. The method of claim 1 , wherein the semiconductor substrate comprises one selected from the group consisting of a bulk semiconductor substrate and a strained semiconductor substrate.
10. The method of claim 6 , wherein forming the channel layer comprises cleaving the semiconductor substrate at a predefined cleaving region within the semiconductor substrate.
11. The method of claim 10 , wherein forming the channel layer further comprises bonding a handle wafer to the respective cap layer of the first and second bottom gate stacks prior to cleaving.
12. The method of claim 1 , wherein the first top gate stack comprises a first top gate dielectric, a first top gate conductor, and a first hard mask layer.
13. The method of claim 12 , wherein the second top gate stack comprises a second top gate dielectric, a second top gate conductor, and a second hard mask layer.
14. The method of claim 13 , further wherein the second top gate conductor is different from the first top gate conductor.
15. The method of claim 14 , wherein the first top gate stack further comprises the second top gate conductor disposed between the first top gate conductor and the first hard mask layer.
16. The method of claim 13 , further wherein the first top gate dielectric and the second top gate dielectric comprise the same top gate dielectric, and wherein the first hard mask layer of the first top gate stack and the second hard mask layer of the second top gate stack comprise a multi-layer hard mask layer.
17. The method of claim 13 , wherein the first top gate conductor is co-planar with the second top gate conductor.
18. The method of claim 1 , further wherein the defining of respective ones of the bottom gate dimensions includes self-aligning of a corresponding defined first bottom gate stack and defined second bottom gate stack with a respective one of the patterned first top gate stack or the patterned second top gate stack.
19. The method of claim 1 , wherein filling comprises one selected from a group consisting of (i) epitaxially growing semiconductor material in the source/drain cavities and (ii) using a deposit and etch back filling of semiconductor material in the source/drain cavities.
20. The method of claim 1 , wherein (a) the first-type transistor region comprises one selected from the group consisting of (i) a first N-type transistor region and (ii) a first P-type transistor region, and (b) the second-type transistor region comprises one selected from the group consisting of (i) the first N-type transistor region, (ii) a second N-type transistor region different from the first N-type transistor region, (iii) the first P-type transistor region, and (iv) a second P-type transistor region different from the first P-type transistor region.