IP Library Granted Patent US 7,045,432
Granted Patent B2
US 7,045,432 · App. 10/771,855 · Granted May 16, 2006

Method for forming a semiconductor device with local semiconductor-on-insulator (SOI)

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Quick Facts
Patent No.
US 7,045,432
App. No.
10/771,855
Granted
May 16, 2006
Kind
B2
Abstract

A semiconductor on insulator transistor is formed beginning with a bulk silicon substrate. An active region is defined in the substrate and an oxygen-rich silicon layer that is monocrystalline is formed on a top surface of the active region. On this oxygen-rich silicon layer is grown an epitaxial layer of silicon. After formation of the epitaxial layer of silicon, the oxygen-rich silicon layer is converted to silicon oxide while at least a portion of the epitaxial layer of silicon remains as monocrystalline silicon. This is achieved by applying high temperature water vapor to the epitaxial layer. The result is a silicon on insulator structure useful for making a transistor in which the gate dielectric is on the remaining monocrystalline silicon, the gate is on the gate dielectric, and the channel is in the remaining monocrystalline silicon under the gate.

Claims (44)

1. A method, comprising:

providing a substrate having an active region that has a top surface;

forming a first layer over the top surface, wherein the first layer comprises an oxygen-rich, semiconductor-material layer;

epitaxially growing a second layer directly on the first layer, wherein the second layer comprises a semiconductor-material layer;

converting the first layer to a semiconductor-oxide layer; and

forming a transistor, wherein a channel of the transistor is formed only in the second layer.

2. The method of claim 1 , wherein a deep source and a deep drain of the transistor are formed only in the second layer.

3. The method of claim 2 , wherein the deep source and the deep drain extend to the semiconductor-oxide layer.

4. The method of claim 2 , wherein the transistor is further characterized as having an elevated source over the deep source and an elevated drain over the deep drain.

5. The method of claim 2 , wherein a gate dielectric of the transistor is formed on the second layer, without an intervening semiconductor layer between the second layer and the gate dielectric.

6. The method of claim 1 , wherein a source and a drain of the transistor extend to the semiconductor-oxide layer.

7. The method of claim 1 , wherein the oxygen-rich, semiconductor-material layer comprises oxygen-rich silicon.

8. The method of claim 1 , wherein the second layer comprises monocrystalline silicon.

9. The method of claim 8 , wherein the first layer comprises oxygen-rich monocrystalline silicon.

10. The method of claim 1 , wherein the converting further comprises forming an oxide layer on a top surface of the second layer.

11. The method of claim 10 , further comprising

removing at least a portion of the oxide layer; and

forming a gate dielectric on the second layer.

12. The method of claim 11 , wherein the transistor further comprises a gate over the gate dielectric, and a deep source and a deep drain in the second layer and laterally spaced from the channel, wherein the channel is under the gate and the deep source and the deep drain are formed only in the second layer.

13. The method of claim 12 , wherein the substrate comprises silicon.

14. The method of claim 12 , wherein the converting comprises introducing high temperature water vapor over the second layer.

15. The method of claim 12 , wherein the transistor is farther characterized as having an elevated source over the deep source and an elevated drain over the deep drain.

16. The method of claim 12 , wherein the gate dielectric is formed directly on the second layer.

17. A method, comprising:

providing a substrate having an active region that has a top surface;

forming a first layer over the top surface, wherein the first layer comprises an oxygen-rich, semiconductor-material layer;

epitaxially growing a second layer directly on the first layer, wherein the second layer comprises a semiconductor-material layer;

converting the first layer to a semiconductor-oxide layer; and

forming a gate dielectric on the second layer, wherein there is no semiconductor layer between the gate dielectric and the second layer.

18. The method of claim 17 , wherein the gate dielectric is formed directly on the second layer.

19. The method of claim 17 , further comprising forming a transistor having a gate over the gate dielectric, a channel under the gate and in the second layer, a deep source and a deep drain in the second layer and laterally spaced from the channel.

20. The method of claim 19 , wherein the deep source and the deep drain extend to the semiconductor-oxide layer.

21. The method of claim 19 , wherein the converting further comprises forming an oxide layer on a top surface of the second layer, and wherein the method further comprises:

removing at least a portion of the oxide layer prior to forming the gate dielectric.

22. The method of claim 17 , wherein the oxygen-rich, semiconductor-material layer comprises oxygen-rich silicon.

23. The method of claim 17 , wherein the second layer comprises monocrystalline silicon, and the first layer comprises oxygen-rich monocrystalline silicon.

24. A method, comprising:

providing a substrate having an active region that has a top surface, a first isolation region, and a second isolation region;

selectively forming a first layer over the top surface between the first and second isolation regions, wherein the first layer comprises an oxygen-rich, semiconductor-material layer;

selectively epitaxially growing a second layer directly on the first layer between the first and second isolation regions, wherein the second layer comprises a semiconductor-material layer, and wherein the second layer is not formed on the first and second isolation regions; and

converting the first layer to a semiconductor-oxide layer.

25. The method of claim 24 , further comprising:

forming a transistor over the second layer, the transistor having a gate dielectric over the second layer, a channel under the gate in the second layer, a deep source and deep drain in the second layer and laterally spaced from the channel, wherein the channel, the deep source, and the deep drain are formed only in the second layer.

26. The method of claim 25 , wherein the deep source and the deep drain extend to the semiconductor-oxide layer.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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323.01(C) ASSIGNMENT OR CHANGE OF NAME IMPROPERLY FILED AND RECORDED BY ANOTHER PERSON AGAINST OWNER'S PATENT Recorded Oct 3, 2019
From: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2017
From: NORTH STAR INNOVATIONS INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
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From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
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To: NORTH STAR INNOVATIONS INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
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To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2004
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