Patent Assignment
Reel/Frame 015360/0718
Assignment of Assignor's Interest
Recorded: 2004-05-07
Received: 2004-11-04
Pages: 37
Assignor
MOTOROLA, INC
Executed: 2004-04-04
Assignee
FREESCALE SEMICONDUCTOR, INC.
6501 WILLIAM CANNON DRIVE WEST, AUSTIN, TX, 78735, UNITED STATES
Covered Properties
(100)
Low Leakage Local Oscillator System
Application:
10/481,977 →
Apparatus and Method for Improving Signal Mismatch Compensation
Application:
10/482,088 →
Prefetch Control in a Data Processing System
Application:
10/631,136 →
Passive Communication Device and Passive Access Control System
Application:
10/481,111 →
Manipulating data streams in data stream processors
Application:
10/475,066 →
Adaptive Radio Frequency (Rf) Filter
Application:
10/481,845 →
Method, program, and apparatus for delegating information processing
Application:
10/475,686 →
State Retention Within a Data Processing System
Application:
10/818,861 →
Method of Attaching a Die to a Substrate
Application:
10/811,581 →
Method for Forming a Semiconductor Device Having a Notched Control Electrode and Structure Thereof
Application:
10/811,461 →
Land Grid Array Packaged Device and Method of Forming Same
Application:
10/807,527 →
Transistor with Reduced Gate-to-Source Capacitance and Method Therefor
Application:
10/807,624 →
Method and Apparatus for Entering a Low Power Mode
Application:
10/806,498 →
Magnetoresistive Random Access Memory Simulation
Application:
10/806,612 →
Load Board with Embedded Relay Tracker
Application:
10/805,954 →
Optimized Reference Voltage Generation Using Switched Capacitor Scaling for Data Converters
Application:
10/804,453 →
Detecting Overcurrents in a Switching Regulator Using a Voltage Dependent Reference
Application:
10/804,450 →
Method of Inhibiting Metal Silicide Encroachment in a Transistor
Application:
10/797,222 →
Selective Tone Event Detector and Method Therefor
Application:
10/795,700 →
Method for forming a semiconductor device having metal silicide
Application:
10/795,847 →
Multiple Burst Protocol Device Controller
Application:
10/792,591 →
Integrated Circuit with Multiple Spacer Insulating Region Widths
Application:
10/790,420 →
Method for Removing Nanoclusters from Selected Regions
Application:
10/787,510 →
Semiconductor Package with Crossing Conductor Assembly and Method of Manufacture
Application:
10/787,288 →
Photolithography Reticle Design
Application:
10/782,566 →
Semiconductor Structure Having Strained Semiconductor and Method Therefor
Application:
10/780,143 →
Method of Making a Semiconductor Device Using Treated Photoresist
Application:
10/779,007 →
Non-Volatile Memory Device with Improved Data Retention and Method Therefor
Application:
10/779,004 →
Method and Apparatus for Processing a Frequency Modulated (Fm) Signal Using an Adaptive Equalizer
Application:
10/779,217 →
Die Encapsulation Using a Porous Carrier
Application:
10/774,977 →
Bidirectional level shifter
Application:
10/774,130 →
Method for Forming a Semiconductor Device with Local Semiconductor-on-Insulator (Soi)
Application:
10/771,855 →
Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
Application:
10/767,998 →
Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
Application:
10/767,996 →
Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
Application:
10/767,994 →
Semiconductor Structure, Semiconductor Device, Communicating Device, Integrated Circuit, and Process for Fabricating the Same
Application:
10/768,108 →
Voltage Regulator with Improved Load Regulation Using Adaptive Biasing
Application:
10/770,149 →
Multi-Bit Non-Volatile Memory Device and Method Therefor
Application:
10/769,228 →
Method for Etching a Quartz Layer in a Photoresistless Semiconductor Mask
Application:
10/766,205 →
Method for Forming a Memory Structure Using a Modified Surface Topography and Structure Thereof
Application:
10/765,804 →
Integrated circuit with conductive grid for power distribution
Application:
10/765,810 →
Real-Time Debug Support for a Dma Device and Method Thereof
Application:
10/764,110 →
Digital Rate Converter
Application:
10/761,158 →
Flipchip Qfn Package and Method Therefor
Application:
10/752,866 →
Method of Packaging an Optical Sensor
Application:
10/752,159 →
Level Shifter
Application:
10/747,748 →
Btsc Encoder and Integrated Circuit
Application:
10/744,619 →
Apparatus for Pulse Testing a Mram Device and Method Therefore
Application:
10/746,014 →
Multi-Strand Substrate for Ball-Grid Array Assemblies and Method
Application:
10/741,065 →
Circuit and Method for Supplying an Electrical a.C. Load
Application:
10/741,055 →
Method and Apparatus for Demodulating a Received Signal Within a Coded System
Application:
10/739,505 →
Stacked Semiconductor Device Assembly and Method for Forming
Application:
10/739,605 →
Blocking layer for silicide uniformity in a semiconductor transistor
Application:
10/739,684 →
Warpage Control of Array Packaging
Application:
10/740,303 →
Method and Apparatus for Reducing Interrupt Latency by Dynamic Buffer Sizing
Application:
10/740,157 →
Synthetic Antiferromagnet Structures for Use in Mtjs in Mram Technology
Application:
10/740,338 →
Slotted Planar Power Conductor
Application:
10/738,815 →
Glitch Removal Circuit
Application:
10/738,433 →
Method of Making a Semiconductor Device Having a Low K Dielectric
Application:
10/736,853 →
Method for Elimination of Excessive Field Oxide Recess for Thin Si Soi
Application:
10/737,115 →
Mram Having Error Correction Code Circuitry and Method Therefor
Application:
10/736,852 →
Reducing Power Consumption During Mram Writes Using Multiple Current Levels
Application:
10/737,114 →
Integrated Circuit Device and Method Therefor
Application:
10/737,116 →
Method and Apparatus for Allocating Entries in a Branch Target Buffer
Application:
10/736,393 →
Method for Reducing Corrosion of Metal Surfaces During Semiconductor Processing
Application:
10/736,395 →
Method and Apparatus for Forming an Soi Body-Contacted Transistor
Application:
10/734,435 →
Method and Apparatus to Implement Dc Offset Correction in a Sigma Delta Converter
Application:
10/731,850 →
Land Grid Array Packaged Device and Method of Forming Same
Application:
10/731,831 →
Adaptive Transmit Power Control System
Application:
10/731,069 →
Mram Device Integrated with Other Types of Circuitry
Application:
10/730,239 →
Method and Apparatus for Controlling the Bandwidth Frequency of an Analog Filter
Application:
10/730,387 →
Hardware for Performing an Arithmetic Function
Application:
10/730,174 →
Method of Forming a Seal for a Semiconductor Device
Application:
10/730,230 →
Method and Apparatus for Dynamically Inserting Gain in an Adaptive Filter System
Application:
10/730,449 →
Derivation of Circuit Block Constraints
Application:
10/728,622 →
Method and Circuit for Multiplying Signals with a Transistor Having More Than One Independent Gate Structure
Application:
10/728,621 →
Inductive Device Including Bond Wires
Application:
10/729,531 →
Apparatus and Method for Time Ordering Events in a System Having Multiple Time Domains
Application:
10/728,398 →
Network Message Filtering Using Hashing and Pattern Matching
Application:
10/721,201 →
Network Message Processing Using Inverse Pattern Matching
Application:
10/721,196 →
Communication Receiver
Application:
10/721,950 →
Multistage dynamic domino circuit with internally generated delay reset clock
Application:
10/718,891 →
Semiconductor Device with Silicided Source/Drains
Application:
10/718,892 →
Semiconductor Device with Magnetically Permeable Heat Sink
Application:
10/716,655 →
Using InGaP pHEMT for power amplifier operation over temperature under digital modulation
Application:
60/523,341 →
Method for Forming a Microwave Field Effect Transistor with High Operating Voltage
Application:
10/716,955 →
Multi-Bit Non-Volatile Integrated Circuit Memory and Method Therefor
Application:
10/716,956 →
High K dielectric film
Application:
60/519,765 →
Integrated Circuit Having Multiple Memory Types and Method of Formation
Application:
10/705,504 →
Transistor Having Three Electrically Isolated Electrodes and Method of Formation
Application:
10/705,317 →
Memory Controller Useable in a Data Processing System
Application:
10/703,924 →
Semiconductor device and method of formation
Application:
10/703,796 →
Compositions and methods for the electroless deposition of NiFe on a work piece
Application:
10/702,909 →
Domino Comparator Capable for Use in a Memory Array
Application:
10/703,657 →
Method of Implementing Polishing Uniformity and Modifying Layout Data
Application:
10/700,883 →
Method and Apparatus for Constraint Graph Based Layout Compaction for Integrated Circuits
Application:
10/332,111 →
Method for Forming Multiple Gate Oxide Thickness Utilizing Ashing and Cleaning
Application:
10/696,079 →
Method of forming an NMOS transistor and structure thereof
Application:
10/696,346 →
Confined Spacers for Double Gate Transistor Semiconductor Fabrication Process
Application:
10/695,163 →
Electromagnetic Noise Shielding in Semiconductor Packages Using Caged Interconnect Structures
Application:
10/694,146 →