IP Library Granted Patent US 6,964,902
Granted Patent B2
US 6,964,902 · App. 10/787,510 · Granted Nov 15, 2005

Method for removing nanoclusters from selected regions

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Quick Facts
Patent No.
US 6,964,902
App. No.
10/787,510
Granted
Nov 15, 2005
Kind
B2
Abstract

Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.

Claims (64)

1. A method, comprising:

providing a semiconductor substrate comprising a periphery region and a nanocluster region;

forming a sacrificial layer overlying a first portion of the semiconductor substrate in the periphery region;

forming an oxide layer overlying a second portion of the semiconductor substrate;

forming a plurality of nanoclusters overlying the sacrificial layer in the periphery region and overlying the semiconductor substrate in the nanocluster region;

removing at least the plurality of nanoclusters overlying the sacrificial layer in the periphery region; and

before removing the sacrificial layer, performing a clean after removing the at least the plurality of nanoclusters overlying the sacrificial layer in the periphery region.

2. The method of claim 1 , further comprising forming a nanocluster device in the nanocluster region and forming a non-nanocluster device in the periphery region.

3. The method of claim 1 , wherein the sacrificial layer has a thickness of at least 10 nanometers.

4. The method of claim 1 , wherein the sacrificial layer comprises at least one of a nitride or an oxide.

5. The method of claim 1 , wherein the sacrificial layer comprises an oxide which etches faster than a thermal oxide.

6. The method of claim 1 , wherein a material of the sacrificial layer is selected such that the plurality of nanoclusters are selectively removable with respect to the sacrificial layer.

7. The method of claim 1 , wherein the sacrificial layer comprises at least one of a pad oxide or a pad nitride.

8. The method of claim 7 , wherein forming the sacrificial layer comprises:

forming at least one of a pad oxide layer or a pad nitride layer over the semiconductor substrate; and

forming isolation regions in the semiconductor substrate using the at least one of the pad oxide layer or the pad nitride layer.

9. The method of claim 1 further comprising:

implementing the clean with a composition that has a basic pH to overcome electrostatic attraction of the plurality of nanoclusters to the sacrificial layer and to the semiconductor substrate.

10. The method of claim 1 further comprising:

implementing the clean with a mechanical action to remove the plurality of nanoclusters from the sacrificial layer and from the semiconductor substrate.

11. A method, comprising:

providing a semiconductor substrate;

forming a sacrificial layer overlying a first portion of the semiconductor substrate by depositing at least one of a nitride-containing layer over the semiconductor substrate, an oxide-containing layer over the semiconductor substrate, or a polysilicon-containing layer over the semiconductor substrate;

forming an oxide layer overlying a second portion of the semiconductor substrate;

forming a plurality of nanoclusters overlying the sacrificial layer and the oxide layer;

removing at least the plurality of nanoclusters overlying the sacrificial layer; and

before removing the sacrificial layer, performing a clean after removing the at least the plurality of nanoclusters overlying the sacrificial layer.

12. A method, comprising:

providing a semiconductor substrate having a periphery region and a nanocluster region;

depositing a first sacrificial layer over the semiconductor substrate in the periphery region and in the nanocluster region;

removing a portion of the first sacrificial layer in the nanocluster region;

forming an insulating layer over the semiconductor substrate in the nanocluster region;

forming a plurality of nanoclusters over the semiconductor substrate, wherein the plurality of nanoclusters is formed over a remaining portion of the first sacrificial layer in the periphery region and over the insulating layer in the nanocluster region;

forming a patterned masking layer over the plurality of nanoclusters in the nanocluster region; and

removing the plurality of nanoclusters which overlie the first sacrificial layer in the periphery region and the remaining portion of the first sacrificial layer.

13. The method of claim 12 , further comprising forming a second sacrificial layer over the semiconductor substrate, wherein depositing the first sacrificial layer comprises depositing the first sacrificial layer over the second sacrificial layer.

14. The method of claim 13 , wherein the first sacrificial layer comprises at least one of a nitride or an oxide, and wherein the second sacrificial layer comprises an oxide.

15. The method of claim 12 , wherein removing the plurality of nanoclusters which overlie the first sacrificial layer in the periphery region and the remaining portion of the first sacrificial layer comprises:

performing a clean after removing the plurality of nanoclusters which overlie the first sacrificial layer in the periphery region and prior to removing the remaining portion of the first sacrificial layer.

16. The method of claim 12 , further comprising forming a nanocluster device in the nanocluster region using at least a portion of the plurality of nanoclusters over the insulating layer in the nanocluster region and forming a non-nanocluster device in the periphery region.

17. A method, comprising:

providing a semiconductor substrate having a periphery region and a nanocluster region;

forming a first pad layer over the semiconductor substrate in the periphery region and in the nanocluster region;

forming isolation regions in the semiconductor substrate using the first pad layer, wherein the isolation regions extend through the first pad layer into the semiconductor substrate;

removing a portion of the first pad layer in the nanocluster region;

forming an insulating layer over the semiconductor substrate in the nanocluster region;

forming a plurality of nanoclusters over the semiconductor substrate, wherein the plurality of nanoclusters is formed over a remaining portion of the first pad layer in the periphery region and over the insulating layer in the nanocluster region;

forming a patterned masking layer over the plurality of nanoclusters in the nanocluster region; and

removing the plurality of nanoclusters which overlie the first pad layer in the periphery region and the remaining portion of the first pad layer.

18. The method of claim 17 , further comprising forming a second pad layer over the semiconductor substrate in the periphery region and in the nanocluster region, wherein the first pad layer is formed over the second pad layer, and wherein forming isolation regions comprises:

forming isolation regions in the semiconductor substrate using the first and second pad layers, wherein the isolation regions extend through the first and second pad layers into the semiconductor substrate.

19. The method of claim 17 , further comprising:

removing a portion of the second pad layer in the nanocluster region prior to forming the insulating layer, and

removing a remaining portion of the second pad layer in the periphery region after removing the plurality of nanoclusters.

20. The method of claim 17 , wherein the first pad layer comprises a nitride and the second pad layer comprises an oxide.

21. The method of claim 17 , further comprising forming a second pad layer over the first pad layer in the periphery region and in the nanocluster region, wherein forming isolation regions comprises:

forming isolation regions in the semiconductor substrate using the first pad layer and the second pad layer, wherein the isolation regions extend through the first pad layer and the second pad layer into the semiconductor substrate.

22. The method of claim 21 , further comprising:

removing the second pad layer in the periphery region and in the nanocluster region prior to removing the portion of the first pad layer in the nanocluster region.

23. The method of claim 21 , wherein the first pad layer comprises an oxide and the second pad layer comprises a nitride.

24. The method of claim 17 , wherein the first pad layer comprises at least one of an oxide or a nitride.

25. The method of claim 17 , wherein removing the plurality of nanoclusters which overlie the first pad layer in the periphery region and the remaining portion of the first pad layer comprises:

performing a clean after removing the plurality of nanoclusters which overlie the first pad layer in the periphery region and prior to removing the remaining portion of the first pad layer.

26. The method of claim 17 , further comprising forming a nanocluster device in the nanocluster region using at least a portion of the plurality of nanoclusters over the insulating layer in the nanocluster region and forming a non-nanocluster device in the periphery region.

Assignments (19)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
From: MOTOROLA, INC
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015360/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2004
From: STEIMLE, ROBERT F.; YATER, JANE A.; CHINDALORE, GOWRISHANKAR L.; SWIFT, CRAIG T.; ANDERSON, STEVEN G.H.; MURALIDHAR, RAMACHANDRAN
To: MOTOROLA, INC.
Reel/Frame 015033/0509 →