Method for elimination of excessive field oxide recess for thin Si SOI
View Patent ↗A method for forming trench isolation in an SOI substrate begins with a pad oxide followed by an antireflective coating (ARC) over the upper semiconductor layer of the SOI substrate. The pad oxide is kept to a thickness not greater than about 100 Angstroms. An opening is formed for the trench isolation that extends into the oxide below the upper semiconductor layer to expose a surface thereof. The pad oxide is recessed along its sidewall with an isotropic etch. This is followed by a thin, not greater than 50 Angstroms, oxide grown along the sidewall of the opening. This grown oxide avoids forming a recess between the ARC and the pad oxide and also avoids forming a void between the surface of the lower oxide layer and the grown oxide. This results in avoiding polysilicon stringers when the subsequent polysilicon gate layer is formed.
1. A method of making a semiconductor device, comprising:
providing a substrate having a semiconductor layer over a first insulating layer;
forming a second insulating layer on the semiconductor layer having a thickness not greater than about 100 Angstroms;
forming an anti-reflective coating (ARC) on the second insulating layer;
etching an opening through the ARC, the second insulating layer, and the semiconductor layer, and into the first insulating layer;
forming a third insulating layer along a sidewall of the opening;
filling the opening with dielectric fill material;
removing the ARC and the second insulating layer; forming a gate dielectric;
forming a conductive layer on the gate dielectric; and
patterning the conductive layer.
2. The method of claim 1 , wherein the filling the opening comprises depositing oxide by high density plasma.
3. The method of claim 1 , wherein the forming the third insulating layer comprises growing oxide.
4. The method of claim 1 , further comprising applying a wet etch prior to forming the third insulating layer and after forming the opening.
5. The method of claim 1 , wherein the conductive layer is polysilicon.
6. The method of claim 1 , wherein the conductive layer further comprises silicide.
7. The method of claim 1 , wherein the second insulating layer has a thickness of not greater than 100 Angstroms.
8. A method of preparing a semiconductor device for formation of a gate, comprising:
providing a semiconductor substrate having a semiconductor layer over a first insulating layer;
forming a second insulating layer on the semiconductor layer having a thickness that is not greater than about 100 Angstroms;
etching an opening through the second insulating layer, and the semiconductor layer, and into the first insulating layer to expose a surface of the first insulating layer;
forming a third insulating layer along a sidewall of the opening without forming a void between the third insulating layer and the surface of the first insulating layer; and
filling the opening with dielectric fill material.
9. The method of claim 8 , further comprising,
forming a fourth insulating layer over the second insulating layer prior to forming the third insulating layer; and
performing an isotropic etch prior to forming the fourth insulating layer to cause a recess in the second insulating layer;
wherein
the forming the third insulating layer avoids formation of an undercut region in the second insulating layer.
10. The method of claim 8 , wherein the third insulating layer is not greater than 50 Angstroms.
11. The method of claim 8 , further comprising:
removing the second insulating layer; and
forming a gate dielectric on the semiconductor layer.
12. A method of making a semiconductor device, comprising:
providing a substrate having a semiconductor layer over a first insulating layer;
forming a second insulating layer on the semiconductor layer;
forming an anti-reflective coating (ARC) on the second insulating layer;
etching an opening through ARC, the second insulating layer, and the semiconductor layer, and into the first insulating layer;
forming a third insulating layer along a sidewall of the opening having a width not greater than 50 Angstroms;
filling the opening with dielectric fill material;
removing the ARC and the second insulating layer;
forming a gate dielectric;
forming a conductive layer on the gate dielectric; and
patterning the conductive layer.
13. The method of claim 12 wherein the second insulating layer has a thickness not greater than 100 Angstroms.
14. The method of claim 12 , wherein filling the opening comprises depositing oxide by high density plasma.
15. The method of claim 12 , wherein the forming the third insulating layer comprises growing oxide.
16. The method of claim 12 , further comprising performing an isotropic etch prior to forming the third insulating layer and after forming the opening.
17. The method of claim 12 , wherein the conductive layer is polysilicon.
18. The method of claim 17 , wherein the conductive layer further comprises suicide.
19. The method of claim 12 , wherein the etching the opening is further characterized as etching no more than 50 Angstroms into the first insulating layer.