Granted Patent B2

US 7,132,303 · App. 10/739,605 · Granted Nov 7, 2006

Abstract

Claims (99)

1. A method comprising:

providing an integrated circuit wafer including a plurality of integrated circuits and a metal layer disposed over each integrated circuit, and a plurality of test probe locations;

forming device landing pads at selected locations of the metal layer to provide locations for electrically coupling each integrated circuit to a corresponding semiconductor device;

electrically coupling a semiconductor device to each integrated circuit via the metal landing pads to provide a plurality of device assemblies, each device assembly including at least one of the integrated circuits and at least one of the semiconductor devices, wherein the test probe locations may be used to test each device assembly while each device assembly is physically coupled to another device assembly by the wafer;

testing each device assembly by contacting test probe locations corresponding to each device assembly with a wafer test probe; and

identifying each device assembly which passes testing.

2. The method of claim 1 further comprising:

trimming each device assembly as necessary after testing each device assembly.

3. The method of claim 1 further comprising:

singulating the device assemblies; and

discarding device assemblies identified as having failed testing.

4. The method of claim 3 further comprising:

packaging the device assemblies which do not fail testing after discarding the device assemblies identified as having failed testing.

5. The method of claim 1 further comprising:

singulating the device assemblies after testing each device assembly.

6. The method of claim 1 wherein the step of providing the integrated circuit comprises:

providing an integrated circuit wafer including a plurality of integrated circuits, each integrated circuit including a final metal circuit interconnect layer of a plurality of metal circuit interconnect layers;

forming a passivation layer over the final metal circuit interconnect layer, the passivation layer not overlying portions of the final metal circuit interconnect layer; and

forming the metal layer over portions of the passivation layer.

7. The method of claim 1 , wherein the test probe locations may be used as wire bond locations.

8. A method comprising:

providing an integrated circuit wafer including a plurality of integrated circuits and a metal layer disposed over each integrated circuit, and a plurality of test probe locations;

forming device landing pads at selected locations of the metal layer to provide locations for electrically coupling each integrated circuit to a corresponding semiconductor device; and

electrically coupling a semiconductor device to each integrated circuit via the metal landing pads to provide a plurality of device assemblies, each device assembly including at least one of the integrated circuits and at least one of the semiconductor devices, wherein the test probe locations may be used to test each device assembly while each device assembly is physically coupled to another device assembly by the wafer;

wherein the providing the integrated circuit comprises:

providing the integrated circuit wafer including the plurality of integrated circuits, each integrated circuit including a final metal circuit interconnect layer of a plurality of metal circuit interconnect layers;

forming a passivation layer over the final metal circuit interconnect layer, the passivation layer not overlying portions of the final metal circuit interconnect layer;

forming the metal layer over portions of the passivation layer; and

forming an organic layer over the passivation layer before forming the metal layer.

9. A method comprising:

providing an integrated circuit wafer including a plurality of integrated circuits and a metal layer disposed over each integrated circuit, and a plurality of test probe locations;

forming device landing pads at selected locations of the metal layer to provide locations for electrically coupling each integrated circuit to a corresponding semiconductor device; and

electrically coupling a semiconductor device to each integrated circuit via the metal landing pads to provide a plurality of device assemblies, each device assembly including at least one of the integrated circuits and at least one of the semiconductor devices, wherein the test probe locations may be used to test each device assembly while each device assembly is physically coupled to another device assembly by the wafer;

wherein the providing the integrated circuit comprises:

providing the integrated circuit wafer including the plurality of integrated circuits, each integrated circuit including a final metal circuit interconnect layer of a plurality of metal circuit interconnect layers;

forming a passivation layer over the final metal circuit interconnect layer, the passivation layer not overlying portions of the final metal circuit interconnect layer; and

forming the metal layer over portions of the passivation layer, wherein the forming the metal layer comprises:

forming a seed metal layer;

patterning the seed metal layer; and

electroplating a second metal on the patterned seed metal layer.

10. The apparatus of claim 9 wherein the second metal is electroplated to a thickness selected to account for at least one of providing a sufficient diffusion bulk characteristic to the second metal, providing power current carrying capability to the second metal, providing bulk for corrosion effect survivability, and minimizing assembly impact damage while still being capable of carrying electric currents to sustain electrical communication between a corresponding integrated circuit and semiconductor device.

11. The apparatus of claim 9 wherein the electroplating is controlled to form a thickness of the second metal within a range from 8 microns to 16 microns with an acceptable thickness variation of plus or minus 4 microns.

12. A method comprising:

providing an integrated circuit wafer including a plurality of integrated circuits and a metal layer disposed over each integrated circuit, and a plurality or test probe locations;

forming device landing pads at selected locations of the metal layer to provide locations for electrically coupling each integrated circuit to a corresponding semiconductor device; and

electrically coupling a semiconductor device to each integrated circuit via the metal landing pads to provide a plurality of device assemblies, each device assembly including at least one of the integrated circuits and at least one of the semiconductor devices, wherein the test probe locations may be used to test each device assembly while each device assembly is physically coupled to another device assembly by the wafer;

wherein the providing the integrated circuit comprises:

providing the integrated circuit wafer including the plurality of integrated circuits, each integrated circuit including a final metal circuit interconnect layer of a plurality of metal circuit interconnect layers;

forming a passivation layer over the final metal circuit interconnect layer, the passivation layer not overlying portions of the final metal circuit interconnect layer; and

forming the metal layer over portions of the passivation layer, wherein the forming the metal layer comprises patterning the metal layer to spatially redistribute contact locations.

13. A method comprising:

providing an integrated circuit wafer including a plurality of integrated circuits and a metal layer disposed over each integrated circuit, and a plurality of test probe locations;

forming device landing pads at selected locations of the metal layer to provide locations for electrically coupling each integrated circuit to a corresponding semiconductor device;

electrically coupling a semiconductor device to each integrated circuit via the metal landing pads to provide a plurality of device assemblies, each device assembly including at least one of the integrated circuits and at least one of the semiconductor devices, wherein the test probe locations may be used to test each device assembly while each device assembly is physically coupled to another device assembly by the wafer;

wherein the providing the integrated circuit comprises:

providing the integrated circuit wafer including the plurality of integrated circuits, each integrated circuit including a final metal circuit interconnect layer of a plurality of metal circuit interconnect layers;

forming a passivation layer over the final metal circuit interconnect layer, the passivation layer not overlying portions of the final metal circuit interconnect layer; and

forming the metal layer over portions of the passivation layer; and

wherein the forming the device landing pads comprises:

forming a solder mask layer over the passivation and metal layers;

forming a masking layer over the solder mask layer, the masking layer being patterned to expose landing pad locations;

removing portions of the solder mask layer exposed by the masking layer; and

removing the masking layer.

14. The method of claim 13 wherein the step of forming the solder mask layer comprises:

sputtering a nonwettable refractory metal layer over the passivation and metal layers.

15. The method of claim 14 wherein the nonwettable refractory metal layer is titanium tungsten.

16. The method of claim 14 wherein the step of removing portions of the solder mask layer comprises:

etching portions of the refractory metal layer exposed by the masking layer to form electrically isolated landing pads.

17. The method of claim 13 wherein:

the step of forming the solder mask layer includes sputtering an adhesion promoter coat over the nonwettable refractory metal layer; and

the step of removing portions of the solder mask layer includes first etching through adhesion promoter coat and then etching portions of the refractory metal layer exposed by the masking layer to form electrically isolated landing pads.

18. A method comprising:

providing an integrated circuit wafer including a plurality of integrated circuits and a metal layer disposed over each integrated circuit, and a plurality of test probe locations;

forming device landing pads at selected locations of the metal layer to provide locations for electrically coupling each integrated circuit to a corresponding semiconductor device;

electrically coupling a semiconductor device to each integrated circuit via the metal landing pads to provide a plurality of device assemblies, each device assembly including at least one of the integrated circuits and at least one of the semiconductor devices, wherein the test probe locations may be used to test each device assembly while each device assembly is physically coupled to another device assembly by the wafer, wherein the electrically coupling comprises:

providing a semiconductor device for each integrated circuit, each semiconductor device including a wafer substrate with first and second surfaces, each semiconductor device including integrated circuitry proximate to the first surface, each semiconductor device including solder structures on the first surface;

placing each semiconductor device over its corresponding integrated circuit with the first surface disposed proximate to the corresponding integrated circuit;

aligning the solder structures with the landing pads;

placing the solder structures in contact with the landing pads; and

reflowing the solder structures.

19. The method of claim 18 wherein the solder structures comprise at least one of solder balls and solder flux paste, and wherein the solder structures comprise a solder material having a melting point not substantially less than an expected peak package mounting reflow temperature.

20. A method comprising:

providing a wafer including a plurality of integrated circuits;

forming a layer of metal over each integrated circuit;

electrically coupling a semiconductor device to each integrated circuit via corresponding metal to provide a plurality of device assemblies, each device assembly including a respective integrated circuit and semiconductor device;

probe testing at least one of the device assemblies while such device assemblies are physically coupled to each other by the wafer.

21. The method of claim 20 wherein the forming the layer of metal over each wafer integrated circuit comprises:

depositing first metal over a first location at a metal landing pad on the integrated circuit; and

depositing metal lateral over a second location lateral to the first location to provide a contact point for the semiconductor device at the second location, the second metal being electrically connected to the first metal.

22. The method of claim 21 wherein the depositing the first metal and the depositing the second metal are performed at substantially the same time.

23. The method of claim 20 wherein the forming of the layer of metal layer is performed so that the metal layer has an average thickness of at least 4 microns to eliminate a need for under bump metal.

24. The method of claim 23 wherein the average thickness is targeted to be within a range from 8 microns to 12 microns.

25. The method of claim 20 further comprising marking each device assembly which fails a probe test.

26. The method of claim 25 further comprising singulating the device assemblies after marking any failed device assemblies.

27. The method of claim 26 wherein the step of singulating comprises:

sawing the wafer between the device assemblies to provide a plurality of separated device assemblies.

28. The method of claim 26 further comprising disposing of marked device assemblies.

29. The method of claim 20 further comprising dicing the device assemblies after probe testing.

30. The method of claim 29 further comprising trimming circuitry of the device assemblies after probe testing and before dicing.

Assignments (19)