Multi-bit non-volatile integrated circuit memory and method therefor
View Patent ↗A non-volatile memory ( 10 ) includes at least two buried bit lines ( 45, 47 ) formed within a semiconductor substrate ( 12 ), a charge storage layer ( 18 ) overlying the semiconductor substrate ( 12 ); a control gate ( 26 ) overlying the charge storage layer ( 18 ); an insulating liner ( 30 ) overlying the control gate; and first and second conductive sidewall spacer control gates ( 32, 34 ). Multiple programmable charge storage regions ( 42 ) and ( 41, 44 ) are created within the charge storage layer ( 18 ) beneath respective ones of the control gate ( 26 ) and the first and second sidewall spacer control gates ( 32, 34 ). Also, the non-volatile memory ( 10 ) is a virtual ground NOR type multi-bit flash EEPROM (electrically erasable programmable read only memory). By using conductive sidewall spacers as the control gates, a very dense multi-bit non-volatile memory can be manufactured.
1. A method of making a non-volatile memory comprising:
providing a semiconductor substrate;
forming at least two buried bit lines within the semiconductor substrate, wherein forming the at least two buried bit lines defines boundaries that delineate the at least two buried bit lines from an active region disposed between the buried bit lines;
providing a charge storage layer overlying the semiconductor substrate;
forming a first control gate overlying the charge storage layer; forming an insulating liner overlying the first control gate; and
forming first and second sidewall spacer control gates adjacent to first and second sidewalls of the first control gate, respectively, the first and second sidewall spacer control gates being separated from the first control gate by at least the insulating liner, wherein multi-bit programmable charge storage regions are created within the charge storage layer beneath respective ones of the control gates.
2. The method of claim 1 , further comprising:
providing a protective layer overlying the charge storage layer.
3. The method of claim 2 , wherein the protective layer includes a nitride layer.
4. The method of claim 1 , wherein the charge storage layer includes a charge storage stack.
5. The method of claim 4 , wherein the charge storage stack includes at least a bottom insulating layer, charge storage layer, and top insulating layer.
6. The method of claim 5 , further wherein the charge storage layer includes at least one selected from the group consisting of a Si 3 N 4 layer, a layer consisting of oxynitride, a layer consisting of a plurality of nanocrystals, a layer consisting of a plurality of nanoclusters, and any combinations thereof.
7. The method of claim 4 , wherein the charge storage stack includes at least one selected from the group consisting of an ONO stack, an oxide nanocrystal oxide stack, and an oxide nanocluster oxide stack.
8. The method of claim 1 , wherein the at least two buried bit lines includes a plurality of buried bit lines.
9. The method of claim 8 , wherein the plurality of buried bit lines are formed subsequent to providing of the charge storage layer.
10. The method of claim 1 , wherein the first control gate includes at least one conductor selected from the group consisting of polysilicon and metal.
11. The method of claim 1 , wherein the first control gate includes polysilicon.
12. The method of claim 1 ; wherein the insulating liner includes an oxide.
13. The method of claim 1 , wherein forming the first control gate includes forming a plurality of first control gates, and
wherein forming the insulating liner includes forming the insulating liner overlying the plurality of first control gates.
14. The method of claim 1 , further wherein the multi-bit programmable charge storage regions are positioned a) underlying the first control gate within the charge storage layer and in a region proximate a boundary of a buried bit line and an active region, and b) underlying the first and second sidewall spacer control gates within the charge storage layer and in a region proximate a boundary of a buried bit line and an active region.
15. The method of claim 1 , wherein forming the first control gate includes forming a plurality of first control gates, and wherein forming the first and second sidewall spacer control gates includes forming a plurality of first and second sidewall spacer control gates adjacent to sidewalls of individual ones of the plurality of first control gates, wherein individual ones of the first and second sidewall spacer control gates are separated from a respective first control gate by at least the insulating liner.
16. The method of claim 1 wherein forming the first control gate includes forming a plurality of first control gates, and wherein forming the first and second sidewall spacer control gates includes forming the first sidewall spacer control gate on a first sidewall of a desired one of the first control gates, wherein the first sidewall spacer control gate extends between the desired one of the first control gates and an adjacent one of the first control gates, and forming the second sidewall spacer control gate on a second sidewall of the desired one of the first control gates, wherein the second sidewall spacer control gate further extends between the desired one of the first control gates and an opposite adjacent one of the first control gates.
17. The method of claim 1 , wherein forming the first and second sidewall spacer control gates includes depositing a conformal layer of conductive material overlying the first control gate followed by anisotropic etching of the conformal layer.
18. The method of claim 17 , wherein the conductive material includes polysilicon.
19. The method of claim 1 , further comprising forming a silicide on the first and second sidewall spacer control gates.
20. The method of claim 1 , further comprising forming a silicide on the first control gate and on the first and second sidewall spacer control gates.
21. The method of claim 1 , wherein the charge storage regions are programmable via a process of hot carrier injection.