IP Library Granted Patent US 7,056,766
Granted Patent B2
US 7,056,766 · App. 10/731,831 · Granted Jun 6, 2006

Method of forming land grid array packaged device

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Quick Facts
Patent No.
US 7,056,766
App. No.
10/731,831
Granted
Jun 6, 2006
Kind
B2
Abstract

A method of packaging an integrated circuit die ( 12 ) includes the steps of forming an array of soft conductive balls ( 14 ) in a fixture ( 30 ) and flattening opposing sides of the balls. The flattened balls are then transferred from the fixture to a mold masking tape ( 36 ). A first side of the IC die is attached to the balls with a die attach adhesive ( 16 ) and then wire bonding pads ( 20 ) on the die are electrically connected directly to respective balls with wires ( 22 ). An encapsulant ( 24 ) is formed over the die, the electrical connections, and a top portion of the formed balls. The tape is removed and adjacent, encapsulated dice are separated via saw singulation. The result is an encapsulated IC having a bottom side with exposed balls.

Claims (38)

1. A method of packaging an integrated circuit die, comprising the steps of:

forming a plurality of soft conductive forms in a fixture, wherein opposing sides of the forms are at least partially flattened;

transferring the formed forms from the fixture to a mold masking tape;

attaching a first side of an integrated circuit die to the mold masking tape, wherein a second side of the die has a plurality of die bonding pads and wherein the die is surrounded by the formed forms;

electrically connecting the die bonding pads to respective ones of the formed forms surrounding the die;

encapsulating the die, the electrical connections, and a top portion of the formed forms with a mold compound; and

removing the mold masking tape such that a bottom portions of the forms are exposed.

2. The method of packaging an integrated circuit die of claim 1 , wherein the forms formed in the fixture are spherical.

3. The method of packaging an integrated circuit die of claim 1 , wherein the forms formed in the fixture are generally rectangular.

4. The method of packaging an integrated circuit die of claim 1 , wherein the forms undergo a mechanical coining step wherein at least two opposing sides of the forms are at least partially flattened.

5. The method of packaging an integrated circuit die of claim 1 , wherein an array of forms is formed in the fixture.

6. The method of packaging an integrated circuit die of claim 1 , further comprising attaching the mold masking tape to a frame.

7. The method of packaging an integrated circuit die of claim 1 , wherein the die attaching step comprises attaching the first side of the die to a plurality of the forms with a die attach adhesive.

8. The method of packaging an integrated circuit die of claim 1 , wherein the electrically connecting step comprises wirebonding the die bonding pads to the respective ones of the forms with a corresponding plurality of wires.

9. The method of packaging an integrated circuit die of claim 8 , wherein in the wirebonding step, the wires penetrate into the forms and are embedded therein.

10. The method of packaging an integrated circuit die of claim 9 , wherein the wires are formed of copper, gold, or an alloy thereof.

11. The method of packaging an integrated circuit die of claim 10 , wherein the forms are formed of a metal that is softer than the wires so that the wires can be embedded into the forms.

12. The method of packaging an integrated circuit die of claim 11 , wherein the metal comprises solder or gold.

13. The method of packaging an integrated circuit die of claim 1 , further comprising the step of saw singulating the encapsulated die from adjacent encapsulated dice.

14. A method of packaging a plurality of integrated circuit dice, comprising the steps of:

forming a plurality of soft conductive forms in a fixture, wherein opposing sides of the forms are at least partially flattened;

transferring the formed forms from the fixture to a mold masking tape;

attaching first sides of the plurality of integrated circuit dice to the mold masking tape, wherein a second side of the dice have a plurality of die bonding pads and wherein each of the die is surrounded by some of the formed forms;

electrically connecting the die bonding pads of the dice to respective ones of the formed forms surrounding the dice;

encapsulating the dice, the electrical connections, and a top portion of the formed forms with a mold compound;

removing the mold masking tape such that a bottom portions of the forms are exposed; and

singulating the encapsulated dice to form individual packaged devices.

15. The method of packaging an integrated circuit die of claim 14 , wherein the forms formed in the fixture are spherical.

16. The method of packaging an integrated circuit die of claim 14 , wherein the forms formed in the fixture are generally rectangular.

17. The method of packaging an integrated circuit die of claim 14 , wherein the forms undergo a mechanical coining step wherein at least two opposing sides of the balls are at least partially flattened.

18. The method of packaging an integrated circuit die of claim 14 , wherein an array of forms is formed in the fixture.

19. The method of packaging an integrated circuit die of claim 14 , further comprising the step of attaching the mold masking tape to a frame.

20. The method of packaging an integrated circuit die of claim 14 , wherein the dice attaching step comprises attaching the first side of the dice to a plurality of the forms with a die attach adhesive.

21. The method of packaging an integrated circuit die of claim 14 , wherein the electrically connecting step comprises wirebonding the die bonding pads to the respective ones of the forms with a corresponding plurality of wires.

22. The method of packaging an integrated circuit die of claim 21 , wherein in the wirebonding step, the wires penetrate the forms and are embedded therein.

23. The method of packaging an integrated circuit die of claim 22 , wherein the wires are formed of copper, gold, or an alloy.

24. The method of packaging an integrated circuit die of claim 23 , wherein the forms are formed of a metal that is softer than the wires so that the wires can be embedded into the forms.

25. The method of packaging an integrated circuit die of claim 24 , wherein the metal comprises solder or gold.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
From: MOTOROLA, INC
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015360/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2003
From: SHIU, HEI MING; CHOW, WAI WONG; XU, NAN
To: MOTOROLA, INC.
Reel/Frame 014785/0852 →