IP Library Granted Patent US 7,585,744
Granted Patent B2
US 7,585,744 · App. 10/730,230 · Granted Sep 8, 2009

Method of forming a seal for a semiconductor device

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Quick Facts
Patent No.
US 7,585,744
App. No.
10/730,230
Granted
Sep 8, 2009
Kind
B2
Abstract

In one embodiment, a reflowable layer 51 is deposited over a semiconductor device 10 and reflowed in an environment having a pressure approximately equal to that of atmosphere to form a seal layer 52 . The seal layer 52 seals all openings 43 in the underlying layer of the semiconductor device 10 . Since the reflow is performed at approximately atmospheric pressure a gap 50 which was coupled to the opening 43 is sealed at approximately atmospheric pressure, which is desirable for the semiconductor device 10 to avoid oscillation. The seal layer 52 is also desirable because it prevents particles from entering the gap 50 . In another embodiment, the seal layer 52 is deposited in an environment having a pressure approximately equal to atmospheric pressure to seal the hole 43 without a reflow being performed.

Claims (33)

1. A method for forming a semiconductor device comprising:

providing a semiconductor substrate;

forming a layer over the semiconductor substrate, wherein a gap is formed between the semiconductor substrate and the layer;

forming an opening within the layer;

forming an insulating layer over the layer at approximately atmospheric pressure to seal the opening and close the gap off to the environment, wherein forming the insulating layer comprises depositing the insulating layer and annealing the insulating layer at approximately atmospheric pressure;

placing the semiconductor substrate into a vacuum environment before forming the insulating layer;

removing the semiconductor substrate from the vacuum environment after forming the insulating layer, wherein forming the insulating layer further comprises depositing the insulating layer; and

reflowing the insulating layer after removing the semiconductor substrate from the vacuum environment.

2. The method of claim 1 , wherein depositing the insulating layer further comprises depositing the insulating layer at approximately atmospheric pressure.

3. The method of claim 2 , wherein depositing is performed by chemical vapor deposition (CVD).

4. The method of claim 1 , wherein annealing comprises a furnace anneal.

5. The method of claim 1 , wherein annealing comprises a localized anneal.

6. The method of claim 1 , wherein annealing further comprises annealing in a phosphorus atmosphere.

7. The method of claim 1 , wherein annealing comprises using a laser.

8. The method of claim 1 , wherein annealing comprises reflowing the insulating layer.

9. The method of claim 1 , wherein forming the layer over the semiconductor substrate comprises forming a polysilicon layer.

10. The method of claim 1 , wherein forming an insulating layer comprises forming a phosphosilicate glass (PSG).

11. A method for forming a semiconductor device comprising:

providing a semiconductor substrate having a first set of extensions and an anchor;

forming a layer coupled to the anchor and able to move relative to the substrate in at least one direction, wherein the layer has a second set of extensions, wherein the first set of extensions and the second set of extensions are interdigitated and form a set of gaps;

placing the semiconductor substrate in a vacuum;

forming an insulating layer over the set of gaps in the vacuum;

removing the semiconductor substrate from the vacuum; and

annealing the insulating layer to seal the set of gaps after removing the semiconductor substrate from the vacuum.

12. The method of claim 1 , wherein forming the layer over the semiconductor substrate comprises forming a conductive layer.

13. The method of claim 11 , forming the insulating layer further comprises depositing the insulating layer.

14. The method of claim 13 , wherein depositing is performed by chemical vapor deposition (CVD).

15. The method of claim 13 , wherein annealing comprises a furnace anneal.

16. The method of claim 13 , wherein annealing comprises a localized anneal.

17. The method of claim 13 , wherein annealing further comprises annealing in a phosphorus atmosphere.

18. The method of claim 13 , wherein annealing comprises using a laser.

19. The method of claim 13 , wherein annealing comprises reflowing the insulating layer.

20. The method of claim 1 , wherein forming the layer comprises forming a polysilicon layer.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0854 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 3, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 023882/0834 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2005
From: GOGOI, BISHNU P.; ROOP, RAYMOND M.; DESAI, HEMANT D.
To: MOTOROLA, INC.
Reel/Frame 016319/0175 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
From: MOTOROLA, INC
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015360/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2003
From: GOGOI, BISHNU P.; ROOP, RAYMOND M.
To: MOTOROLA, INC.
Reel/Frame 014779/0261 →