Method and apparatus for reducing interrupt latency by dynamic buffer sizing
View Patent ↗A method for reducing interrupt latency in a data processing system wherein a storage device is provided having a predetermined maximum number of storage locations. Data execution circuitry is coupled to the storage device for providing data to the storage device and storing the data in the storage device. Interrupt control circuitry is coupled to the data execution circuitry, wherein the interrupt control circuitry interrupts the data execution circuitry. The data stored in the storage device is completely outputted, thereby having an associated interrupt latency resulting from the output of the stored data. The storage capacity of the storage device is changed dynamically to minimize the interrupt latency. The storage device has a utilization value that varies between a predetermined minimum number of storage locations and the predetermined maximum number of storage locations based upon an operating mode of the data processing system.
1. A method for reducing interrupt latency in a data processing system comprising:
providing a storage device having a predetermined maximum number of storage locations;
coupling data execution circuitry to the storage device for providing data to the storage device and storing the data in the storage device;
coupling interrupt control circuitry to the data execution circuitry, the interrupt control circuitry interrupting the data execution circuitry;
completing outputting stored data in the storage device, thereby having an associated interrupt latency resulting from outputting of the stored data; and
dynamically changing storage utilization of the storage device to minimize the interrupt latency, the storage device having a utilization value that varies between a predetermined minimum number of storage locations and the predetermined maximum number of storage locations based upon an operating mode of the data processing system.
2. The method of claim 1 further comprising:
enabling the interrupt control circuitry to receive interrupt requests having a plurality of differing priorities; and
implementing the operating mode of the system to be associated with priority of enabled interrupt requests.
3. The method of claim 2 further comprising:
providing a size limit register, the size limit register having one or more fields associated with at least one or more priorities for the enabled interrupt requests having the plurality of differing priorities, each of the one or more fields storing a limit value that defines the utilization value for each corresponding one or more fields.
4. The method of claim 3 further comprising providing the size limit register within the storage device.
5. The method of claim 1 further comprising:
providing a size limit register, the size limit register storing a limit value that defines the utilization value of the storage device, the limit value being dynamically modifiable during operation of the data processing system.
6. The method of claim 5 further comprising providing the size limit register within the storage device.
7. The method of claim 1 further comprising:
providing a size limit register, the size limit register having one or more fields that store a predetermined limit value associated with a predetermined process of the data processing system, the limit value being dynamically modifiable during operation of the data processing system.
8. The method of claim 7 further comprising providing the size limit register within the storage device.
9. A data processing system comprising:
a storage device having a predetermined maximum number of storage locations;
data execution circuitry coupled to the storage device for providing data to the storage device and storing the data in the storage device; and
interrupt control circuitry coupled to the data execution circuitry, the interrupt control circuitry interrupting the data execution circuitry, the interrupt control circuitry permitting stored data in the storage device to be fully emptied thereby resulting in an interrupt latency, the interrupt control circuitry dynamically changing storage utilization of the storage device to minimize the interrupt latency, the storage device having a variable number of storage locations that varies between a predetermined minimum number of storage locations and the predetermined maximum number of storage locations based upon an operating mode of the data processing system.
10. The data processing system of claim 9 wherein the interrupt control circuitry receives interrupt requests that have a plurality of differing priorities and wherein the operating mode of the data processing system is dependent upon a current priority of interrupt request.
11. The data processing system of claim 9 wherein the interrupt control circuitry has a plurality of inputs, each of the plurality of inputs receiving a predetermined one of interrupt requests that have a plurality of differing priorities.
12. The data processing system of claim 11 further comprising:
a size limit storage means that has one or more fields associated with at least one or more priorities of the interrupt requests that have the plurality of differing priorities, the one or more fields storing a limit value that defines the variable number of storage locations for a corresponding one or more fields.
13. The data processing system of claim 12 wherein the size limit storage means further comprises a register within the storage device.
14. The data processing system of claim 11 further comprising:
a size limit storage means for storing a limit value that defines utilization of the storage device, the limit value being dynamically modifiable during operation of the data processing system.
15. The data processing system of claim 14 wherein the size limit storage means further comprises a register within the storage device.
16. The data processing system of claim 11 further comprising:
size limit storage means, the size limit storage means having one or more fields that store a predetermined limit value associated with a predetermined process of the data processing system, the predetermined limit value being dynamically modifiable during operation of the data processing system.
17. The data processing system of claim 16 wherein the size limit storage means further comprise a register within the storage device.
18. A method for reducing interrupt latency in a data processing system comprising:
providing storage means having a predetermined maximum number of storage locations;
coupling data execution means to the storage means for providing data to the storage means and storing the data in the storage means;
coupling interrupt control means to the data execution means, the interrupt control means interrupting the data execution means;
completing outputting stored data in the storage means, thereby having an associated interrupt latency resulting from outputting of the stored data; and
dynamically changing storage utilization of the storage means to minimize the interrupt latency, the storage means having a utilization value that varies between a predetermined minimum number of storage locations and the predetermined maximum number of storage locations based upon an operating mode of the data processing system.
19. The method of claim 18 further comprising:
enabling the interrupt control means to receive interrupt requests having a plurality of differing priorities;
implementing the operating mode of the system to be associated with priority of enabled interrupt requests; and
providing a size limiter means, the size limiter means having one or more fields associated with at least one or more priorities for the enabled interrupt requests having the plurality of differing priorities, each of the one or more fields storing a limit value that defines the utilization value for each corresponding one or more fields.
20. The method of claim 18 further comprising:
providing a size limiter means, the size limiter means defining the utilization value of the storage means, the utilization value being dynamically modifiable during operation of the data processing system.
21. The method of claim 18 further comprising:
providing a size limiter means, the size limiter means having one or more fields that store a predetermined limit value associated with a predetermined process of the data processing system, the predetermined limit value being dynamically modifiable during operation of the data processing system.