IP Library Granted Patent US 6,903,004
Granted Patent B1
US 6,903,004 · App. 10/736,853 · Granted Jun 7, 2005

Method of making a semiconductor device having a low K dielectric

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,903,004
App. No.
10/736,853
Granted
Jun 7, 2005
Kind
B1
Abstract

A low K dielectric layer and a cap for the low K dielectric layer are formed in situ using the same silicon precursors but at different precursor ratios. The low K dielectric is deposited with precursors that are useful for making a low K dielectric. Trenches are formed in the low K dielectric and are filled by a metal layer. Chemical mechanical processing (CMP) is utilized to remove the metal outside the trench while the cap aids planarity outside the trench.

Claims (46)

1. A method comprising:

forming a dielectric overlying a substrate of a wafer, wherein the forming the dielectric further comprises:

forming a low K dielectric layer overlying the substrate by a chemical vapor deposition (CVD) process using a silicon precursor, wherein a dielectric constant of the low K dielectric layer is less than 3.0;

forming a second dielectric layer overlying the low K dielectric layer by a CVD process using the silicon precursor;

forming a void in the dielectric including in the low K dielectric layer and the second dielectric layer;

depositing a material over the wafer including depositing the material in the void;

removing portions of the material exterior to the void by polishing the wafer with a chemical mechanical polishing (CMP) process wherein the polishing removes at least some of the second dielectric layer.

2. The method of claim 1 wherein the silicon precursor includes a OctaMethylCycloTetraSiloxane(OMCTS) material.

3. The method of claim 1 wherein the silicon precursor includes a TetraMethylCycloTetraSiloxane(TMCTS) material.

4. The method of claim 1 wherein the silicon precursor includes molecules having a cyclic siloxane structure.

5. The method of claim 1 wherein the forming the low K dielectric layer and the forming the second dielectric layer includes maintaining continuous plasma using the silicon precursor.

6. The method of claim 5 wherein the maintaining the continuous plasma further includes providing plasma using the silicon precursor and oxygen at a first ratio of silicon precursor to oxygen during the forming the low K dielectric layer and providing plasma using the silicon precursor and oxygen at a second ratio of silicon precursor to oxygen during the forming the second dielectric layer, wherein the first ratio is greater than the second ratio.

7. The method of claim 1 wherein:

the forming the low K dielectric layer includes providing plasma using the silicon precursor and oxygen at a first ratio of silicon precursor to oxygen;

wherein the forming the second dielectric layer includes providing plasma using the silicon precursor and oxygen at a second ratio of silicon precursor to oxygen;

wherein the first ratio is greater than the second ratio.

8. The method of claim 7 wherein the first ratio is greater than or equal to 2 milligrams per minute of silicon precursor to 1 standard cubic centimeter of oxygen.

9. The method of claim 7 wherein the second ratio is less than or equal to 1 milligram per minute of silicon precursor to 1 standard cubic centimeter of oxygen.

10. The method of claim 1 wherein the low K dielectric layer has a dielectric constant of less than 2.8.

11. The method of claim 1 wherein the low K dielectric layer has a thickness of 2000 Angstroms or greater.

12. The method of claim 1 wherein the chemical vapor deposition (CVD) process used in forming the low K dielectric layer includes is performed with a deposition in a range of 4-10 Torr.

13. The method of claim 1 wherein no K value degrading processes are performed on the low K dielectric layer prior to the forming the second dielectric layer.

14. The method of claim 1 wherein the material is a conductive material.

15. The method of claim 1 wherein the low K dielectric layer is formed on a surface of the wafer including on conductive material and on another dielectric.

16. The method of claim 1 wherein the second layer has a hardness and the low K dielectric layer has a hardness, wherein the hardness of the second dielectric layer is greater than the hardness of the low K dielectric layer.

17. The method of claim 1 wherein a portion of the second dielectric layer remains after the removing portions of the material exterior to the void.

18. A method of making a dielectric comprising:

forming a low K dielectric layer overlying a wafer substrate by a chemical vapor deposition (CVD) that includes providing plasma using a silicon precursor and oxygen at a first ratio of silicon precursor to oxygen, the silicon precursor including at least one of a OctaMethylCycloTetraSiloxane(OMCTS) material and a TetraMethylCycloTetraSiloxane(TMCTS) material, wherein a dielectric constant of the low K dielectric layer is less than 3.0, and

forming a second dielectric layer on the low K dielectric layer by a CVD process that includes providing plasma using the silicon precursor and oxygen at a second ratio of silicon precursor to oxygen;

wherein the first ratio is greater than the second ratio.

19. The method of claim 18 wherein the first ratio is greater than or equal to 2 milligrams per minute of silicon precursor to 1 standard cubic centimeter of oxygen.

20. The method of claim 18 wherein the second ratio is less than or equal to 1 milligrams per minute of silicon precursor to 1 standard cubic centimeter of oxygen.

21. A semiconductor device comprising:

a substrate;

an interconnect overlying the substrate, the interconnect comprising:

a dielectric overlying the substrate, the dielectric including a low K dielectric layer and a second dielectric layer overlying the low K dielectric layer, the low K dielectric layer having a dielectric constant of less than 3.0, the second dielectric layer having a silicon to carbon intensity ratio of less than about 175 to 1 by time of flight secondary ion mass spectroscopy; and

a conductive interconnect structure located in a void of the dielectric, the void including a void in the low K dielectric layer and a void in the second dielectric layer;

wherein the second dielectric layer and the conductive interconnect structure each have a surface substantially coplanar with each other.

22. A method comprising:

forming a dielectric overlying a substrate of a wafer, wherein the forming the dielectric further comprises:

forming a low K dielectric layer overlying the substrate by a chemical vapor deposition (CVD) that includes providing plasma using a silicon precursor and oxygen at a first ratio of silicon precursor to oxygen, the silicon precursor including at least one of a OctaMethylCycloTetraSiloxane(OMCTS) material and a TetraMethylCycloTetraSiloxane(TMCTS) material;

forming a second dielectric layer overlying the low K dielectric layer by a CVD process that includes providing plasma using the silicon precursor and oxygen at a second ratio of silicon precursor to oxygen;

wherein the first ratio is greater than the second ratio;

forming a void in the dielectric including in the low K dielectric layer and the second dielectric layer;

depositing a material over the wafer including depositing the material in the void; and

removing portions of the material exterior to the void by polishing the wafer with a chemical mechanical polishing (CMP) process wherein the polishing removes at least some of the second dielectric layer.

Assignments (19)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
From: MOTOROLA, INC
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015360/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2003
From: SPENCER, GREGORY S.; TURNER, MICHAEL D.
To: MOTOROLA, INC.
Reel/Frame 014809/0328 →