Method for forming a semiconductor device having a notched control electrode and structure thereof
View Patent ↗A method for forming a semiconductor device ( 10 ) includes providing a substrate ( 20 ) having a surface; forming an insulating layer ( 22 ) over the surface of the substrate ( 20 ); forming a first patterned conductive layer ( 30 ) over the-insulating layer ( 22 ); forming a second patterned conductive layer ( 32 ) over the first patterned conductive layer ( 30 ); forming a patterned non-insulating layer ( 34 ) over the second patterned conductive layer ( 32 ); and selectively removing portions of the first and second patterned conductive layers ( 30, 32 ) to form a notched control electrode for the semiconductor device ( 10 ).
1. A method for forming a semiconductor device comprising:
providing a substrate having a surface;
forming an insulating layer over the surface of the substrate;
forming a first patterned conductive layer over the insulating layer;
forming a second patterned conductive layer over the first patterned conductive layer;
forming a patterned non-insulating layer over the second patterned conductive layer; and
selectively removing portions of the first and second patterned conductive layers to form a notched control electrode for the semiconductor device.
2. The method of claim 1 , further comprising implanting source/drain regions in the substrate.
3. The method of claim 1 , further comprising forming a halo implant in the substrate.
4. The method of claim 1 , wherein forming the patterned non-insulating layer comprises forming the patterned non-insulating layer of polysilicon.
5. The method of claim 1 , wherein the first patterned conductive layer comprises one of tantalum carbide, tantalum nitride, nickel silicide, tantalum silicide, cobalt suicide, or tungsten.
6. The method of claim 1 , wherein the first patterned conductive layer comprises one or titanium nitride, rhenium, platinum, ruthenium oxide, rhodium suicide, palladium suicide, or tungsten carbon nitride.
7. The method of claim 1 , wherein the first patterned conductive layer is formed to a thickness of between 1 and 40 nanometers.
8. The method of claim 1 , wherein the second patterned conductive layer comprises silicon germanium.
9. The method of claim 1 , wherein die second patterned conductive layer comprises one of doped silicon germanium, doped silicon, doped silicon carbide, silicide, metal carbide or metal nitride.
10. The method of claim 1 , wherein the insulating layer comprises one of hafnium oxide, aluminum nitride, aluminum oxide, tantalum pentoxide, barium titanium oxide, lanthanum aluminate or zirconium oxide, or combinations thereof.
11. The method of claim 1 , wherein selectively removing portions of the first and second patterned conductive layers further comprises:
selectively etching a predetermined portion of an exposed lateral edge of the second patterned conductive layer; and
oxidizing an exposed portion of the first patterned conductive layer.
12. The method of claim 1 , wherein selectively removing portions of the first and second patterned conductive layers further comprises:
selectively etching a predetermined portion of an exposed lateral edge of the second patterned conductive layer; and
selectively etching an exposed portion of the first patterned conductive layer of the using a soft etch semiconductor manufacturing process.
13. The method of claim 1 , further comprising forming a second insulating layer in the notches and on the opposite sides of the notched control electrode.
14. The method of claim 1 , further comprising forming sidewall spacers on the second insulating layer on the opposite sides and in the notches of the notched control electrode.
15. The method of claim 1 , wherein after selectively removing portions of the first and second patterned conductive layers, the first and second patterned conductive layers have lengths that arc substantially equal.