Blocking layer for silicide uniformity in a semiconductor transistor
A semiconductor device and fabrication process includes forming a gate dielectric overlying a semiconductor substrate and a gate electrode overlying the gate dielectric. The gate electrode includes an interface between a first portion of the gate electrode and a second portion of the gate electrode. A silicide is then formed overlying the gate electrode. The presence of the gate electrode interface substantially prevents the silicide from spiking into or through the gate electrode to encroach upon or contact the underlying gate dielectric. Forming the gate electrode may include forming a polysilicon first gate electrode layer and forming an amorphous silicon layer over the polysilicon first gate electrode layer. Forming the second gate electrode layer may include forming a SiGe first sublayer and a polysilicon second sublayer.
1 . A semiconductor fabrication process, comprising:
forming a gate dielectric overlying a semiconductor substrate;
forming a gate electrode by:
depositing a first gate electrode layer in contact with the gate dielectric, wherein the first gate electrode layer is selected from the group consisting of polysilicon and amorphous silicon;
depositing a silicon germanium layer in contact with the first gate electrode layer; and
depositing a third gate electrode layer in contact with the silicon germanium layer, wherein the third gate electrode layer material is the same as the first gate electrode material; and
forming a silicide in contact with the third gate electrode.
2 . The method of claim 1 , wherein depositing the first and third gate electrode layers comprises depositing a polysilicon layer at a temperature in the range of approximately 600 to 650 C.
3 . The method of claim 1 , wherein depositing the first and third gate electrode layers comprises depositing an amorphous silicon layer at a temperature of less than approximately 580 C.
4 . The method of claim 1 , wherein forming the third gate electrode layer comprises forming the third gate electrode layer in situ with forming the first gate electrode layer by lowering the temperature of the deposition chamber.
5 . (canceled)
6 . The method of claim 1 , wherein the SiGe comprises polycrystalline SiGe.
7 . The method of claim 6 , wherein forming the second gate electrode layer is achieved in situ by introducing a germanium bearing species into a deposition chamber after forming the first gate electrode layer.
8 . A semiconductor device, comprising:
a gate dielectric overlying a semiconductor substrate;
a gate electrode comprising a first gate electrode layer in contact with a second gate electrode layer wherein the first gate electrode layer contacts the gate dielectric and wherein the first and second gate electrode layers are both selected from the group consisting of polysilicon and amorphous silicon and wherein the first and second gate electrode layers differ; and
a silicide in contact with the second layer.
9 . The device of claim 8 , wherein the gate electrode includes:
a polysilicon first gate electrode layer; and
an amorphous silicon second gate electrode layer.
10 . The device of claim 8 , wherein the first gate electrode layer is an amorphous silicon layer and wherein the second gate electrode layer is a polysilicon layer.
11 - 12 . (canceled)
13 . The device of claim 8 , wherein the first gate electrode layer is an amorphous silicon layer and wherein the second gate electrode layer is a polycrystalline silicon layer.
14 . The device of claim 8 , wherein the silicide comprises CoSi 2 .
15 . A semiconductor fabrication process, comprising:
forming a gate electrode overlying a gate dielectric layer overlying a semiconductor substrate, wherein the gate electrode includes first and second layers in contact with one another wherein the first layer contacts the gate electrode;
wherein at least one of the first and second layers includes polycrystalline silicon; and
forming a silicide in contact with the second gate electrode layer.
16 . (canceled)
17 . The process of claim 15 , wherein the first gate electrode layer comprises polycrystalline silicon and wherein the second gate electrode layer comprises amorphous silicon.
18 . The process of claim 15 , wherein the first gate electrode layer comprises amorphous silicon and wherein the second gate electrode layer comprises polycrystalline silicon.
19 . (canceled)
20 . The process of claim 15 , wherein forming the silicide comprises forming a CoSi 2 silicide.