Non-volatile memory device with improved data retention and method therefor
View Patent ↗A semiconductor device ( 30 ) comprises an underlying insulating layer ( 34 ), an overlying insulating layer ( 42 ) and a charge storage layer ( 36 ) between the insulating layers ( 34, 42 ). The charge storage layer ( 36 ) and the overlying insulating layer ( 42 ) form an interface, where at least a majority of charge in the charge storage layer ( 36 ) is stored. This can be accomplished by forming a charge storage layer ( 36 ) with different materials such as silicon and silicon germanium layers or n-type and p-type material layers, in one embodiment. In another embodiment, the charge storage layer ( 36 ) comprises a dopant that is graded. By storing at least a majority of the charge at the interface between the charge storage layer ( 36 ) and the overlying insulating layer ( 42 ), the leakage of charge through the underlying insulating layer is decreased allowing for a thinner underlying insulating layer ( 34 ) to be used.
1. A non-volatile memory cell comprising:
a semiconductor substrate;
a tunnel oxide formed over the semiconductor substrate;
a floating gate formed over the tunnel oxide comprising a plurality of charge, a first layer comprising silicon and having a depletion region and a second layer comprising silicon and germanium and having an accumulation region, wherein the accumulation region stores a greater concentration of the plurality of charge than the depletion region;
an insulating layer formed on the floating gate, wherein the insulating layer is in physical contact with the accumulation region, and the depletion region is between the accumulation region and the tunnel oxide; and
a control gate formed over the insulating layer, wherein most of the plurality of charge is stored at an interface between the floating gate and the insulating layer, and away from the tunnel oxide.
2. The non-volatile memory cell of claim 1 , wherein the first layer is a material with a higher bandgap than the second material.
3. The non-volatile memory cell of claim 1 , wherein the greater concentration of charge is at least a majority of charge.
4. The non-volatile memory cell of claim 3 , wherein the depletion region stores substantially none of the plurality of charge.
5. The non-volatile memory cell of claim 1 , wherein the depletion region comprises a first dopant concentration and the accumulation region comprises a second dopant concentration, wherein the second dopant concentration is greater than the first dopant concentration.
6. The non-volatile memory cell of claim 1 , wherein the insulating layer is an oxide-nitride-oxide stack.