Integrated circuit with multiple spacer insulating region widths
View Patent ↗An integrated circuit with both P-channel transistors ( 823 ) and N-channel transistors ( 821 ) with different spacer insulating region widths. In one example, the outer sidewall spacer ( 321 ) of the N-channel transistors is removed while the P-channel regions ( 115 ) are masked such that the spacer insulating region widths of the N-channel transistors is less than the spacer insulating region widths of the P-channel transistors. Also, the drain/source silicide regions ( 805 ) of the N-channel transistors are located closer to the gates ( 117 ) of those transistors than the P-channel source/drain suicide regions ( 809 ) are located to the gates ( 119 ) of those transistors. Providing the P-channel transistors with greater spacer insulating widths and greater distances between the source/drain silicide regions and gates may increase the relative compressive stress of the channel region of the P-channel transistors relative the stress of the channel region of the N-channel transistors, thereby increasing the performance of the P-channel transistors.
1. A method comprising:
providing a substrate;
forming, over the substrate, a first gate for an N-channel transistor and a second gate for a P-channel transistor;
forming a first sidewall spacer for the N-channel transistor lateral to the first gate and a second sidewall spacer for the P-channel transistor lateral to the second gate;
forming a third sidewall spacer for the N-channel transistor lateral to the first sidewall spacer and a fourth sidewall spacer for the P-channel transistor lateral to the second sidewall spacer;
providing a first mask over the first gate;
implanting dopants, while the first mask is over the first gate, of a first conductivity type into the substrate;
removing the first mask after the implanting the dopants of the first conductivity type;
providing a second mask over the second gate;
implanting dopants, while the second mask is over the second gate, of a second conductivity type into the substrate;
removing the third sidewall spacer while the second mask is over the second gate;
forming a first silicide region in the substrate for the N-channel transistor, wherein the first silicide region is substantially aligned with the first sidewall spacer; and
forming a second silicide region in the substrate for the P-channel transistor, wherein the second silicide region is substantially aligned with the fourth sidewall spacer.
2. The method of claim 1 , further comprising:
forming a first liner over the first gate and a second liner over the second gate prior to the forming the first sidewall spacer and the second sidewall spacer, and
forming a third liner over the first sidewall spacer and a fourth liner over the second sidewall spacer prior to the forming the third sidewall spacer and the fourth sidewall spacer.
3. The method of claim 2 wherein:
the third liner is of a first material;
the third sidewall spacer is of a second material that is selectably eatable from the first material.
4. The method of claim 3 wherein the first material includes an oxide and the second material includes a nitride.
5. The method of claim 1 , wherein the first sillicide region is a first distance from the first gate and wherein the second silicide region is a second distance from the second gate, wherein the second distance is greater than the first distance.
6. The method of claim 1 , wherein the providing the first mask occurs prior to the providing the second mask.
7. The method of claim 1 , wherein the providing the first mask occurs after the providing the second mask.
8. The method of claim 1 further comprising:
implanting dopants in a first region and a second region of the substrate of the second conductivity type for forming a first extension and a second extension for the N-channel transistor, respectively; and
implanting dopant in a third region and a fourth region of the substrate of the first conductivity type for forming a third extension and a fourth extension for the P-channel transistor, respectively.
9. The method of claim 8 , wherein:
the implanting dopants in the substrate of the second conductivity type are utilized to form a first doped region and a second region in the substrate that are in contact with the first extension and second extension, respectively; and
the implanting dopants of the first conductivity type are utilized to form a third doped region and a fourth doped region in the substrate in contact with the third extension and the fourth extension, respectively.
10. The method of claim 1 , further comprising implanting dopants, while the second mask is over the second gate and after removing the third sidewall spacer, of the second conductivity type into the substrate.
11. The method of claim 1 , wherein the first gate comprises polysilicon.
12. The method of claim 1 , wherein the first gate comprises a metal.
13. The method of claim 1 , wherein the substrate is characterized as having a silicon on an insulator configuration.
14. The method of claim 1 wherein:
the forming the first side wall spacer and the second sidewall spacer further includes depositing a first layer of spacer material over the substrate and etching the first layer with a dry etch;
the forming the third side wall spacer and the fourth sidewall spacer further includes depositing a second layer of spacer material over the substrate and etching the second layer with a dry etch.
15. The method of claim 14 wherein the first layer and the second layer include nitride.