Method of forming a FINFET structure
View Patent ↗A semiconductor device ( 10 ) such as a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting ( 32 ) of a source ( 14 ) electrode and a drain ( 16 ) electrode adjacent to an intervening gate ( 18 ) and channel ( 23 ) connected via source/drain extensions ( 22, 24 ) which form a fin. At small dimensions, ion implanting may cause irreparable crystal damage to any thin areas of silicon such as the fin area. To permit a high concentration/low resistance source/drain extension, a sacrificial doping layer ( 28, 30 ) is formed on the sides of the fin area. Dopants from the sacrificial doping layer are diffused into the source electrode and the drain electrode using heat. Subsequently a substantial portion, or all, of the sacrificial doping layer is removed from the fin.
1. A method for forming a semiconductor structure, comprising:
providing a substrate;
providing a semiconductor structure over the substrate comprising a semiconductor fin, a first source/drain contact region adjacent to a first end of the semiconductor fin, a second source/drain contact region adjacent to a second end of the semiconductor fin, and a gate feature along a middle portion of a first side of the semiconductor fin;
forming a first sacrificial doping layer on the first side of the semiconductor fin between the first source/drain contact region and the gate feature and a second sacrificial doping layer on the first side of the semiconductor fin between the second source/drain contact region and the gate feature;
heating the first and second sacrificial doping layers;
after the step of heating, removing at least a substantial portion of the first sacrificial doping layer and at least a substantial portion of the second sacrificial doping layer.
2. The method of claim 1 further comprising:
implanting the first and second sacrificial doping layers with source/drain dopants prior to the step of heating.
3. The method of claim 1 wherein the step of forming the first and second sacrificial doping layers is further characterized as depositing the first and second sacrificial doping layers in situ doped with source/drain dopants.
4. The method of claim 1 further comprising replacing the gate feature with a gate.
5. The method of claim 1 , wherein the gate feature is a gate separated from the semiconductor fin by a gate dielectric.
6. The method of claim 1 further comprising forming a sidewall spacer adjacent to the gate feature prior to the step of forming the first and second sacrificial doping layers.
7. The method of claim 1 wherein the semiconductor fin is of a material that is selectively etchable with respect to the first and second sacrificial doping layers.
8. The method of claim 1 wherein the semiconductor fin comprises silicon, the first and second sacrificial doping layers comprises silicon germanium, and removing at least the substantial portion of the first sacrificial doping layer and the second sacrificial doping layer comprises applying an etchant that is selective between silicon and silicon germanium.
9. The method of claim 8 , wherein the etchant comprises NH 4 and H 2 O 2 .
10. The method of claim 1 wherein the step of forming the first and second sacrificial doping layers comprises epitaxially growing silicon germanium.
11. The method of claim 1 further comprising implanting the first and second sacrificial doping layers with source/drain dopants at an angle that deviates from vertical by at least ten degrees, wherein vertical is with respect to a top surface of the substrate.
12. The method of claim 1 , wherein:
the step of providing the semiconductor structure is further characterized as providing the gate feature along a middle portion of a second side of the semiconductor fin; and
the step of forming the first and second sacrificial doping layers is further characterized as forming the first sacrificial doping layer on the second side of the semiconductor fin between the gate feature and the first source/drain contact region and as forming the second sacrificial doping layer on the second side of the semiconductor fin between the gate feature and the second source/drain contact region.
13. The method of claim 1 , wherein the first and second sacrificial doping layers are further characterized as being a selected one of the group consisting of amorphous and polycrystalline.
14. A method for forming a FinFET structure, comprising:
providing a substrate;
providing a semiconductor fin having a height and a width, wherein the height is at least five times greater than the width;
providing a gate feature along a middle portion of the semiconductor fin, the gate feature having a first side and a second side;
forming a first sacrificial doping layer on the semiconductor fin adjacent to and spaced from the first side of the semiconductor fin and a second sacrificial doping layer on the semiconductor fin adjacent to and spaced from the second side of the gate feature, wherein the first and second sacrificial doping layers are doped with a source/drain dopant material;
heating the first and second sacrificial doping layers to cause some of the source/drain dopants to diffuse into the semiconductor fin; and
applying an etchant to the first and second sacrificial doping layers.
15. The method of claim 14 further comprising:
forming a sidewall spacer adjacent to the gate feature prior to forming the first and second sacrificial doping layers.
16. The method of claim 14 wherein the etchant is selective between the semiconductor fin and the first and second sacrificial doping layers.
17. The method of claim 14 , wherein the step of forming the first and second sacrificial doping regions is further characterized as implanting the first and second sacrificial doping layers with the source/drain dopant material.
18. The method of claim 14 wherein the step of forming the first and second sacrificial doping layers is further characterized as depositing the first and second sacrificial doping layers in situ doped with the source/drain dopant material.
19. A method of forming a semiconductor device structure, comprising:
forming a semiconductor feature having a height, width, and length protruding from a substrate, the semiconductor feature characterized as having a first side of the height and length on a first side of the width and a second side of the height and length on a second side of the width;
forming a gate feature in a middle portion of the semiconductor feature on the first side, the second side, and the width, whereby a first source/drain extension region and a second source/drain extension region are uncovered by the gate feature;
forming a sidewall spacer on the gate feature;
forming a dopant-transferring material on the first and second source/drain extension regions;
heating the dopant-transferring material; and
substantially removing the dopant-transferring material.
20. The method of claim 19 wherein:
the dopant-transferring material is doped by a selected one of the group consisting of implanting and in-situ doping;
the sidewall spacer comprises a dielectric material; and
the dopant-transferring material is characterized as being comprised of a different type of material than that of the semiconductor feature.