IP Library Granted Patent US 7,435,625
Granted Patent B2
US 7,435,625 · App. 11/257,802 · Granted Oct 14, 2008

Semiconductor device with reduced package cross-talk and loss

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Quick Facts
Patent No.
US 7,435,625
App. No.
11/257,802
Granted
Oct 14, 2008
Kind
B2
Abstract

Structure and method are provided for plastic encapsulated semiconductor devices having reduced package cross-talk and loss. Semiconductor die are first coated with a buffer region having a lower dielectric constant ε and/or lower loss tangent δ than the plastic encapsulation. The encapsulation surrounds the buffer region providing a solid structure. The lower ε buffer region reduces the stray capacitance and therefore the cross-talk between electrodes on or coupled to the die. The lower δ buffer region reduces the parasitic loss in the encapsulation. Low ε and/or δ buffer regions can be achieved using low density organic and/or inorganic materials. Another way is to disperse hollow microspheres or other fillers in the buffer region. An optional sealing layer formed between the buffer region and the encapsulation can mitigate any buffer layer porosity. The buffer region desirably has ε less than about 3.0 and/or δ less than about 0.005.

Claims (17)

1. A method of encapsulating a semiconductor die, comprising:

mounting the die on a lead-frame;

adding particles of a filler to a resin, wherein the particles of the filler have a mix of filler sizes, and the particles of the filler are tightly packed within the resin;

covering a portion of the die with a buffer region of a first dielectric constant and first loss tangent, wherein the buffer region includes the resin and the filler packed within the resin;

placing the lead-frame with the die and buffer region in a mold suitable for plastic encapsulation, wherein the die and buffer region are located in a cavity in the mold; and

placing a plastic encapsulant in the cavity of the mold to substantially fill the cavity of the mold around the lead frame, die and buffer region with a plastic material of a second dielectric constant and a second loss tangent, wherein at least the second dielectric constant is larger than the first dielectric constant or the second loss tangent is larger than the first loss tangent.

2. The method of claim 1 , further comprising, after the step of covering the portion of the die, curing the buffer region.

3. The method of claim 1 , wherein the step of covering the portion of the die comprises covering the portion of the die with a buffer region material having the filler therein comprising hollow microspheres.

4. The method of claim 3 , wherein the step of covering the portion of the die comprises covering the portion of the die with a buffer region material having a first dielectric constant less than about 80% of the second dielectric constant.

5. The method of claim 1 , further comprising, between the step of covering the portion of the die and the step of placing the plastic encapsulant in the cavity, covering the buffer region with a sealing layer.

6. The method of claim 1 , wherein the step of covering the portion of the die comprises covering the portion of the die with a material that includes an organic material.

7. The method of claim 6 , wherein the step of covering the portion of the die comprises covering the portion of the die with a material that includes an inorganic material.

8. The method of claim 1 , wherein the step of covering the portion of the die comprises covering the portion of the die with a buffer region material having the filler therein comprising finely divided styrene.

9. The method of claim 1 , wherein the step of covering the portion of the die comprises covering the portion of the die with a buffer region material having the filler therein comprising a plastic.

10. The method of claim 1 , wherein the step of covering the portion of the die comprises covering the portion of the die with a buffer region material having the filler therein comprising glass fragments.

11. The method of claim 1 , wherein the step of covering the portion of the die comprises covering the portion of the die with a buffer region material having the filler therein comprising ceramic fragments.

12. The method of claim 1 , wherein the step of covering the portion of the die comprises covering the portion of the die with a buffer region material having the filler therein comprising filler having particles equal to 300 micro-meters or less.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
323.01(C) ASSIGNMENT OR CHANGE OF NAME IMPROPERLY FILED AND RECORDED BY ANOTHER PERSON AGAINST OWNER'S PATENT Recorded Oct 3, 2019
From: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 052459/0656 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2017
From: NORTH STAR INNOVATIONS INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 041717/0736 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0807 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →