IP Library Granted Patent US 7,579,279
Granted Patent B2
US 7,579,279 · App. 11/670,176 · Granted Aug 25, 2009

Method to passivate conductive surfaces during semiconductor processing

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Quick Facts
Patent No.
US 7,579,279
App. No.
11/670,176
Granted
Aug 25, 2009
Kind
B2
Abstract

A method for processing semiconductor wafers is disclosed. A solution is applied to a semiconductor wafer to prevent dendrites and electrolytic reactions at the surface of metal interconnects. The solution can be applied during a CMP process or during a post CMP cleaning process. The solution may include a surfactant and a corrosion inhibitor. In one embodiment, the concentration of the surfactant in the solution is less than approximately one percent by weight and the concentration of the corrosion inhibitor in the solution is less than approximately one percent by weight. The solution may also include a solvent and a cosolvent. In an alternate embodiment, the solution includes a solvent and a cosolvent without the surfactant and corrosion inhibitor. In one embodiment, the CMP process and post CMP cleaning process can be performed in the presence of light having a wavelength of less than approximately one micron.

Claims (45)

1. A method for processing semiconductor wafers, comprising:

subjecting a semiconductor wafer to a CMP process, wherein the CMP process comprises buffing a surface of the semiconductor wafer;

subjecting the semiconductor wafer to a post CMP cleaning process in the presence of light having a wavelength of less than approximately one micron;

applying a solution to the semiconductor wafer during the CMP process wherein the solution comprises a solvent and a cosolvent, and applying the solution is performed at least during the buffing; and

applying the solution to the semiconductor wafer during the post CMP cleaning process.

2. The method of claim 1 , wherein the post CMP cleaning process comprises applying a mechanical action to a surface of the semiconductor wafer, and wherein applying the solution is performed at least during the applying the mechanical action to the surface of the semiconductor wafer.

3. The method of claim 1 , wherein the solvent comprises one of water, alcohol, glycol, acetone, acetonitrile, or propylene carbonate.

4. The method of claim 1 , wherein the cosolvent is a different from the solvent and comprises one of alcohol, glycol, acetone, acetonitrile, or propylene carbonate.

5. The method of claim 4 , wherein a concentration of the cosolvent in the solution is in a range of approximately 0.5 percent by weight to approximately 50 percent by weight.

6. The method of claim 4 , wherein a concentration of the cosolvent in the solution is in a range of approximately 1 percent by weight to approximately 10 percent by weight.

7. The method of claim 1 , wherein the solution further comprises a surfactant, the surfactant comprising one of a polyethylene glycol (PEG), block copolymer, or polypropylene glycol.

8. The method of claim 7 , wherein a concentration of the surfactant in the solution is less than approximately one percent by weight.

9. The method of claim 7 , wherein the solution further comprises a corrosion inhibitor, the corrosion inhibitor comprising one of benzene triazole, caffeine, theophiline, bipyridyl, or triazole.

10. The method of claim 9 , wherein a concentration of the corrosion inhibitor in the solution is less than approximately one percent by weight.

11. The method of claim 1 , wherein:

the solvent comprises one of water, alcohol, glycol, acetone, acetonitrile, or propylene carbonate;

the cosolvent is different than the solvent and comprises one of alcohol, glycol, acetone, acetonitrile, or propylene carbonate; and

the solution further comprises:

surfactant comprising one of a polyethyleneglycol (PEG), block copolymer, or polypropyleneglycol; and

a corrosion inhibitor comprising one of benzene triazole, caffeine, theophiline, bipyridyl, or triazole.

12. A method for processing semiconductor wafers, comprising:

polishing a semiconductor wafer on a first platen to remove a portion of a first conductive layer using a first solution, wherein the first solution comprises a first surfactant, a first solvent, and an oxidizing agent;

transferring the semiconductor wafer to a second platen;

polishing the semiconductor wafer on the second platen to remove a portion of a second conductive layer using a second solution, wherein the second conductive layer is thinner than the first conductive layer;

transferring the semiconductor wafer to a third platen;

buffing the semiconductor wafer using the third platen using a third solution, wherein the third solution comprises a second solvent, a co-solvent that is different than the second solvent, a second surfactant, and a corrosion inhibitor, wherein the buffing the semiconductor wafer is part of a CMP process; and

subjecting the semiconductor wafer to a post CMP cleaning process in the presence of light having a wavelength of less than approximately one micron, wherein the third solution is applied to the semiconductor wafer during the post CMP cleaning process.

13. The method of claim 12 , wherein the first solution is the same as the second solution.

14. The method of claim 12 , wherein polishing the semiconductor wafer on the second platen ends when the process endpoints on a barrier layer under the second conductive layer.

15. The method of claim 12 , wherein the third solution comprises:

the second solvent comprises one of water, alcohol, glycol, acetone, acetonitrile, or propylene carbonate;

the cosolvent comprises one of alcohol, glycol, acetone, acetonitrile, or propylene carbonate;

the second surfactant comprising one of a polyethyleneglycol (PEG), block copolymer, or polypropyleneglycol; and

the corrosion inhibitor comprising one of benzene triazole, caffeine, theophiline, bipyridyl, or triazole.

16. A method for processing semiconductor wafers, comprising:

polishing a semiconductor wafer on a first platen;

transferring the semiconductor wafer to a second platen;

polishing the semiconductor wafer on the second platen;

transferring the semiconductor wafer to a third platen; and

buffing the semiconductor wafer using the third platen and a chemical composition comprising:

a surfactant comprising one of a polyethyleneglycol (PEG), block copolymer, or polypropyleneglycol;

a corrosion inhibitor comprising one of benzene triazole, caffeine, theophiline, bipyridyl, or triazole;

a solvent comprising one of water, alcohol, glycol, acetone, acetonitrile, or propylene carbonate; and

a cosolvent, different from the solvent, comprising one of alcohol, glycol, acetone, acetonitrile, or propylene carbonate; and wherein the buffing the semiconductor wafer is part of a CMP process;

subjecting the semiconductor wafer to a post CMP cleaning process, wherein the chemical composition is applied to the semiconductor wafer during the post CMP cleaning process and subjecting the semiconductor wafer to the post CMP cleaning process occurs in the presence of light having a wavelength of less than approximately one micron.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
323.01(C) ASSIGNMENT OR CHANGE OF NAME IMPROPERLY FILED AND RECORDED BY ANOTHER PERSON AGAINST OWNER'S PATENT Recorded Oct 3, 2019
From: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 052459/0656 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2017
From: NORTH STAR INNOVATIONS INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 041717/0736 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0854 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0640 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 3, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 023882/0834 →
SECURITY AGREEMENT Recorded Sep 19, 2007
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 019847/0804 →