Electronic device and a process for forming the electronic device
View Patent ↗An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.
1. A process of forming a electronic device comprising a gated diode, wherein the process comprises:
forming a junction within a semiconductor material;
forming a first conductive member, wherein after forming the junction and forming the first conductive member, the first conductive member is spaced apart from and adjacent to the junction, wherein the first conductive member includes a first gate electrode of the gated diode; and
forming a second conductive member spaced apart from and adjacent to the junction, wherein:
the second conductive member is electrically insulated from the first conductive member;
the second conductive member includes a second gate electrode of the gated diode;
forming the second conductive member is performed after forming the junction; and
the gated diode comprises the junction, the first gate electrode, and the second gate electrode.
2. The process of claim 1 , wherein forming the junction is performed before forming the first conductive member, before performing the second conductive member, or any combination thereof.
3. The process of claim 1 , wherein forming the junction comprises forming a p-i-n diode.
4. The process of claim 1 , further comprising:
forming a first signal line electrically connected to the first conductive member; and
forming a second signal line electrically connected to the second conductive member.
5. The process of claim 4 , wherein the first signal line is configured to be controlled independently from the second signal line.
6. The process of claim 1 , further comprising:
forming a first gate dielectric between the first conductive member and the junction; and
forming a second gate dielectric between the second conductive member and the junction.
7. The process of claim 1 , wherein forming the junction within the semiconductor material further comprises forming a semiconductor fin.
8. The process of claim 1 , wherein forming the junction comprises forming a graded junction.
9. The process of claim 1 , wherein forming the junction comprises forming a pn junction.
10. The process of claim 9 , wherein forming the junction is performed such that a junction diode structure of the gated diode has a single pn junction.
11. The process of claim 1 , wherein forming the junction comprises forming a junction between an intrinsic semiconductor material and a doped semiconductor material.
12. The process of claim 1 , wherein forming the junction, forming the first conductive member, and forming the second conductive member is performed such that the first gate electrode and the second gate electrode lie along opposite sides of a junction diode structure that includes the junction.
13. The process of claim 3 , wherein forming the junction is performed such that a junction diode structure of the gated diode has a single p-type region, a single intrinsic region, and a single n-type region.
14. The process of claim 1 , wherein forming the first conductive member, forming the second conductive member, or both comprises depositing the semiconductor material over the junction.
15. The process of claim 1 , wherein forming the first conductive member, forming the second conductive member, or both comprises depositing a metal-containing material over the junction.
16. The process of claim 1 , wherein forming the first conductive member is performed after forming the junction.
17. The process of claim 16 , further comprising forming a gate dielectric layer after forming the first conductive member and before forming the junction.
18. The process of claim 1 , further comprising forming a gate dielectric layer after forming the junction, wherein after forming the first conductive member and forming the second conductive member, different parts of the gate dielectric layer lie between the junction and each of the first and second gate electrodes.
19. The process of claim 1 , wherein forming the junction is performed such that a junction diode structure of the gated diode comprises a fin diode including the junction.
20. The process of claim 1 , further comprising:
forming a first gate dielectric layer, such that after forming the junction, forming the first gate dielectric layer, and forming the first conductive member, the first gate dielectric lies between the first conductive member and the junction; and
forming a second gate dielectric layer before forming the second conductive member.