IP Library Granted Patent US 8,743,970
Granted Patent B2
US 8,743,970 · App. 12/422,684 · Granted Jun 3, 2014

Video decoding with error detection and concealment

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Quick Facts
Patent No.
US 8,743,970
App. No.
12/422,684
Granted
Jun 3, 2014
Kind
B2
Abstract

A system and method of decoding input video information is disclosed which includes performing error detection for each video block of a frame, determining whether a scene change occurs for the frame, and when an error is detected in a video block, performing spatial concealment by concealing error of the erroneous video block using neighboring video information within the frame when the erroneous video block is intraframe encoded or when a scene change is detected for the frame, or performing temporal concealment by replacing the erroneous video block with a reference video block from a reference frame when the erroneous video block is interframe encoded and when a scene change is not detected for the frame. The method may further include detecting false frames based on comparing current and new frame number and picture order count values of a new slice.

Claims (68)

1. A method of decoding input video information, comprising:

performing error detection for each video block of a frame;

determining whether a scene change occurs for the frame;

tracking a relative amount of interframe mode video blocks for the frame;

determining error concealment for the frame on a block-by-block basis, comprising:

when an error is detected in a video block of the frame, determining spatial concealment of the erroneous video block when the erroneous video block is intraframe encoded, or when a scene change is detected for the frame and the relative amount of interframe mode video blocks does not achieve a first predetermined threshold, and otherwise determining temporal concealment of the erroneous video block; and

enabling spatial concealment and temporal concealment to be determined within the same frame.

2. The method of claim 1 , wherein said determining whether a scene change occurs for the frame comprises determining whether an amount of intraframe mode video blocks achieves a predetermined percentage of the frame.

3. The method of claim 1 , wherein said determining whether a scene change occurs for the frame comprises determining that a number of intraframe mode video blocks divided by a total number of decoded video blocks achieves a second predetermined threshold.

4. The method of claim 1 , further comprising:

detecting an error of the input video information;

receiving a new frame number from a new video slice; and

decoding the new video slice as part of a current frame when an error of the input video information is detected and when a prior frame number is not zero and is equal to the new frame number.

5. The method of claim 1 , further comprising:

detecting an error of the input video information;

receiving a new frame number and a new picture order count from a new video slice; and

decoding the new video slice as part of a current frame when an error of the input video information is detected and when the prior frame number is not zero and a prior picture order count is equal to the new picture order count.

6. The method of claim 1 , further comprising:

detecting an error of the input video information;

receiving a new frame number from a new video slice; and

decoding the new video slice as part of a current frame when an error of the input video information is detected, when the new frame number is not zero and when a difference between the prior frame number and the new frame number is greater than a predetermined maximum number.

7. The method of claim 1 , further comprising performing spatial concealment comprising interpolating pixel values across the erroneous video block by combining relative portions of first and second aligned pixel values of adjacent video blocks within the frame based on relative position within the erroneous video block.

8. The method of claim 1 , wherein said performing spatial concealment comprises padding pixel values by copying an aligned pixel value of an adjacent video block within the frame across the erroneous video block.

9. The method of claim 1 , further comprising performing spatial concealment comprising:

when an upper adjacent video block and a lower adjacent video block of an erroneous video block are both valid within the frame, interpolating pixel values across the erroneous video block between a lower pixel line of the upper adjacent video block and an upper pixel line of the lower adjacent video block; and

when only one of the upper adjacent video block and the lower adjacent video block is valid within the frame, padding pixel values across the erroneous video block based on an adjacent pixel line of the valid adjacent video block.

10. The method of claim 9 , wherein said performing spatial concealment further comprises:

when the upper adjacent video block and the lower adjacent video block are both invalid and a left adjacent video block and a right adjacent video block of the erroneous video block are both valid, interpolating pixel values across the erroneous video block between a right pixel line of the left adjacent video block and a left pixel line of the right adjacent video block; and

when only one of the right adjacent video block and the left adjacent video block is valid, padding pixel values across the erroneous video block based on an adjacent pixel line of the valid adjacent video block.

11. An error detection and concealment system for a video decoder which is configured to decode each video block of a frame of input video information based on encoding type, said error detection and concealment system comprising:

a scene change detection circuit which is configured to determine a scene change for the frame based on relative amount of intraframe type video blocks;

a tracking circuit which is configured to track a relative amount of interframe type video blocks;

an error detection circuit which is configured to indicate whether there is an error in each video block and

to determine error concealment for the frame on a block-by-block basis, wherein said error concealment circuit is configured to determine spatial concealment for an erroneous video block when said erroneous video block is intraframe encoded, or when a scene change is detected for the frame and said relative amount of interframe mode video blocks does not achieve a first predetermined threshold, and which is configured to otherwise determine temporal concealment of said erroneous video block; and

wherein said error detection circuit is configured to determine spatial concealment and temporal concealment within the same frame.

12. The error detection and concealment system of claim 11 , wherein:

said tracking circuit tracks said relative amount of intraframe type video blocks; and

wherein said scene change detection circuit comprises a comparator circuit which detects a scene change when an amount of intraframe type video blocks achieves a second predetermined threshold.

13. The error detection and concealment system of claim 11 , further comprising a frame error concealment circuit which receives a new frame number and a new picture order count from a new video slice, and which, when an error is detected in the input video information, indicates that said new video slice is to be decoded as part of the frame when a prior frame number is not zero and is equal to said new frame number, when said prior frame number is not zero and a prior picture order count is equal to said new picture order count, or when said new frame number is not zero and when a difference between said prior frame number and said new frame number is greater than a predetermined maximum number.

14. The error detection and concealment system of claim 11 , further comprising an error concealment circuit which performs said spatial concealment by either interpolating pixel values between valid adjacent video blocks on either side of said erroneous video block or by padding pixel values from one valid adjacent video block.

15. The error detection and concealment system of claim 14 , wherein said error concealment circuit performs interpolation by combining relative portions of first and second aligned pixel values based on relative position within said erroneous video block, and wherein said error concealment circuit performs padding by copying an aligned pixel value across said erroneous video block.

16. A video decoder, comprising:

a video decoder circuit which is configured to decode video blocks of a frame based on encoding type;

a scene change detection circuit which is configured to determine whether a scene change is occurring for said frame based on relative amount of intraframe encoded video blocks;

an error memory;

a tracking circuit which is configured to track a relative amount of interframe encoded video blocks;

an error detection circuit which is configured to determine error concealment type for said frame on a block-by-block basis and to program said error memory to indicate whether there is an error in each video block and a type of error concealment between spatial error concealment and temporal error concealment based on video block encoding type and whether a scene change is occurring; and

an error concealment circuit which is configured to perform spatial concealment for an erroneous video block by incorporating neighboring video information within said frame when said erroneous video block is intraframe encoded, or when a scene change is detected for the frame and said relative amount of interframe encoded video blocks does not achieve a predetermined threshold, and which otherwise is configured to perform temporal concealment by replacing said erroneous video block with a corresponding video block from a reference frame;

wherein said error concealment circuit is configured to perform both spatial concealment and temporal concealment within said frame.

17. The video decoder of claim 16 , further comprising a frame error concealment circuit which receives a new frame number and a new picture order count from a new video slice, and which, after detecting an error of input video information, causes said video decoder circuit to decode said new video slice as part of the frame when a prior frame number is not zero and is equal to said new frame number, when said prior frame number is not zero and a prior picture order count is equal to said new picture order count, or when said new frame number is not zero and when a difference between said prior frame number and said new frame number is greater than a predetermined maximum number.

18. The method of claim 1 , while decoding a frame of the input video information, further comprising:

counting a number of video blocks received for decoding so far in the frame and providing a video block count;

counting a number of intraframe mode video blocks received for decoding so far in the frame and providing an intraframe count;

counting a number of interframe mode video blocks received for decoding so far in the frame and providing an interframe count;

determining that an erroneous video block is a lost video block when its coding mode is unknown; and

when the video block count achieves a predetermined percentage of the frame, providing a scene change indication when the intraframe count divided by the video block count achieves a first predetermined threshold, and providing an intermode indication when the interframe count divided by the video block count achieves a second predetermined threshold;

said determining spatial concealment comprising determining spatial concealment of the erroneous video block when the erroneous video block is intraframe encoded, or when the scene change indication is provided and the erroneous video block is a lost video block, or when the erroneous video block is interframe encoded when the scene change indication is provided and the intermode indication is not provided; and

said determining temporal concealment comprising determining temporal concealment of the erroneous video block when the erroneous video block is not intraframe encoded and the scene change indication is not provided, or when the erroneous video block is interframe encoded and the scene change indication and the interframe indication are both provided.

19. The error detection and concealment system of claim 11 , wherein:

said tracking circuit is configured to count a number of video blocks received for decoding so far in the frame and to provide a video block count indicative thereof, to count a number of intraframe mode video blocks received for decoding so far in the frame and to provide an intraframe count indicative thereof, to count a number of interframe mode video blocks received for decoding so far in the frame and to provide an interframe count indicative thereof, and to determine whether a video block is a lost video block when its coding mode is unknown;

wherein said scene change detection circuit comprises a comparator circuit which is configured to provide a scene change indication when said intraframe count divided by said video block count achieves a first predetermined threshold after said video block count has achieved a predetermined percentage of the frame, and to provide an intermode indication when said interframe count divided by said video block count achieves a second predetermined threshold after said video block count has achieved a predetermined percentage of the frame;

wherein said error detection circuit is configured to determine spatial concealment of said erroneous video block when said erroneous video block is intraframe encoded, or when said erroneous video block is a lost video block and said scene change indication is provided, or when said erroneous video block is interframe encoded when said scene change indication is provided and said intermode indication is not provided; and

wherein said error concealment circuit is further configured to determine temporal concealment of said erroneous video block when said erroneous video block is not intraframe encoded and said scene change indication is not provided, or when said erroneous video block is interframe encoded and said scene change indication and said interframe indication are both provided.

20. The video decoder of claim 16 , wherein:

said tracking circuit is configured to count a number of video blocks received for decoding so far in the frame and provides a video block count, to count a number of intraframe mode video blocks received for decoding so far in the frame and provides a corresponding intraframe count, to count a number of interframe mode video blocks received for decoding so far in the frame and provides a corresponding interframe count, and to determine whether a video block is a lost video block when its coding mode is unknown;

wherein said scene change detection circuit comprises a comparator circuit which is configured to provide a scene change indication when said intraframe count divided by said video block count achieves a first predetermined threshold after said video block count has achieved a predetermined percentage of the frame, and to provide an intermode indication when said interframe count divided by said video block count achieves a second predetermined threshold after said video block count has achieved a predetermined percentage of the frame;

wherein said error concealment circuit is configured to perform spatial concealment of said erroneous video block when said erroneous video block is intraframe encoded, or when said erroneous video block is a lost video block and said scene change indication is provided, or when said erroneous video block is interframe encoded when said scene change indication is provided and said intermode indication is not provided; and

wherein said error concealment circuit is further configured to perform temporal concealment of said erroneous video block when said erroneous video block is not intraframe encoded and said scene change indication is not provided, or when said erroneous video block is interframe encoded and said scene change indication and said interframe indication are both provided.

Assignments (24)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
323.01(C) ASSIGNMENT OR CHANGE OF NAME IMPROPERLY FILED AND RECORDED BY ANOTHER PERSON AGAINST OWNER'S PATENT Recorded Oct 3, 2019
From: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 052459/0656 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2017
From: NORTH STAR INNOVATIONS INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 041717/0736 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0823 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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