IP Library Granted Patent US 8,617,935
Granted Patent B2
US 8,617,935 · App. 13/220,891 · Granted Dec 31, 2013

Back side alignment structure and manufacturing method for three-dimensional semiconductor device packages

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Quick Facts
Patent No.
US 8,617,935
App. No.
13/220,891
Granted
Dec 31, 2013
Kind
B2
Abstract

A mechanism for accurate alignment of semiconductor package back side interconnect processing is provided. As semiconductor die are placed in position for an encapsulated panel, two or more alignment die having fiducial markings formed on the back, or non-active, side of those die are also placed in the panel. Once all the die and other components have been placed for the panel, the panel is encapsulated using an encapsulant. Excess encapsulant, if any, is removed by a process such as backgrinding. The back grinding process exposes the back side of the alignment die and the fiducial features on those alignment die. The fiducial features on the alignment die can then be used for alignment of backside processing operations on the panel.

Claims (51)

1. A method for packaging integrated circuit die, the method comprising:

forming a panel comprising

one or more integrated circuit die,

a plurality of alignment die, wherein

the alignment die comprise fiducial markings on a major surface of the alignment die, and

the panel has first and second major surfaces;

encapsulating the one or more integrated circuit die in the panel with an active surface of each integrated circuit die being exposed at the first major surface of the panel; and

encapsulating the plurality of alignment die in the panel with the major surface of the alignment die being exposed at the second major surface of the panel, wherein

the fiducial markings are exposed at the second major surface of the panel, and

said encapsulating the integrated circuit die and the plurality of alignment die is performed using an encapsulant.

2. The method of claim 1 further comprising:

exposing the major surface of the alignment die, wherein said exposing results in the alignment die fiducials filled with encapsulant.

3. The method of claim 2 wherein

said exposing comprises performing a backgrind of the second major surface of the panel; and

the backgrind is performed to a depth sufficient to expose the major surface of the alignment die and less than a depth of the fiducial markings on the major surface of the alignment die.

4. The method of claim 2 wherein the major surface of the alignment die comprises a material having high contrast with the encapsulant filling the fiducials.

5. The method of claim 4 wherein the major surface material of the alignment die comprises one of silicon, metal, and a dielectric.

6. The method of claim 1 further comprising:

exposing the major surface of the alignment die, wherein

said exposing comprises performing said encapsulating the plurality of alignment die such that an encapsulation thickness is the alignment die thickness.

7. The method of claim 6 further comprising:

forming the fiducial markings using one of laser drilling, engraving, or molding.

8. The method of claim 6 further comprising:

pre-filling the fiducial markings with a material that provides a high contrast with the major surface of the alignment die.

9. The method of claim 1 wherein said forming the panel further comprises:

placing the plurality of alignment die in a plurality of corresponding areas for the panel; and

forming the fiducial markings on the major surface of each of the alignment die subsequent to said placing.

10. The method of claim 9 wherein said forming comprises using a laser drill.

11. The method of Clam 9 wherein said forming provides fiducial markings having an aspect ratio of a width of the fiducial markings to a depth of the fiducial markings of less than one.

12. The method of claim 1 wherein said forming the panel further comprises:

placing the plurality of alignment die in a plurality of corresponding areas for the panel, wherein the fiducial markings are provided on the alignment die prior to said placing.

13. The method of claim 12 wherein the alignment die are molded with the fiducial markings.

14. The method of claim 1 wherein the plurality of alignment die have a thickness between the major surface of the alignment die and the first major surface of the panel that is greater than a thickness of the plurality of integrated circuit die.

15. The method of claim 2 wherein, prior to said exposing the major surface of the plurality of alignment die, the plurality of alignment die have a thickness between the major surface of the alignment die and the first major surface of the panel that is greater than a thickness of the panel between the first and second major surfaces of the panel subsequent to said exposing.

16. The method of claim 1 wherein the plurality of alignment die comprises two alignment die.

17. The method of claim 1 further comprising:

filling the alignment die fiducials with a material having an optical contrast with a material comprising the major surface of the alignment die, wherein said filling is performed prior to said encapsulating the plurality of alignment die in the panel.

18. The method of claim 1 wherein the alignment die are one of active die having an active surface opposing the major surface of the alignment die, or dummy die having no active surface opposing the major surface of the alignment die.

19. The method of claim 1 further comprising:

forming a dielectric layer over the second major surface of the panel;

forming a plurality of holes in the dielectric layer to expose conductive structures accessible on the second major surface of the panel, wherein said forming the plurality of holes is performed using the alignment die fiducial markings for alignment of the holes; and

forming one or more electrical interconnects over the second major surface of the panel, using the plurality of holes.

20. A method for packaging integrated circuit die, the method comprising:

forming a panel comprising

a plurality of alignment die, wherein

the alignment die comprise alignment markings on a major surface of the alignment die, and

the panel has first and second major surfaces;

forming the alignment markings on the alignment die by one of drilling, laser drilling, molding, or printing; and

encapsulating the plurality of alignment die in the panel with the major surface of the alignment die being exposed at the second major surface of the panel, wherein

the fiducial markings are exposed at the second major surface of the panel, and

the fiducial markings contrast with the major surface of the alignment die subsequent to being exposed.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
323.01(C) ASSIGNMENT OR CHANGE OF NAME IMPROPERLY FILED AND RECORDED BY ANOTHER PERSON AGAINST OWNER'S PATENT Recorded Oct 3, 2019
From: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 052459/0656 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2017
From: NORTH STAR INNOVATIONS INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 041717/0736 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0477 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027621/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2011
From: XU, JIANWEN; GONG, ZHIWEI; HAYES, SCOTT M.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 026827/0095 →