Patent Assignment
Reel/Frame 037357/0387
Patent Release
Recorded: 2015-12-21
Pages: 37
Assignor
CITIBANK, N.A., AS COLLATERAL AGENT
Executed: 2015-12-07
Assignee
FREESCALE SEMICONDUCTOR, INC.
6501 WILLIAM CANNON DRIVE WEST, AUSTIN, TEXAS, 78735
Covered Properties
(641)
Receiver with Automatic Gain Control
PCT:
PCT/US2010/041187 ↗
Pulse Width Modulation Frequency Conversion
PCT:
PCT/US2010/044067 ↗
Mems Device with Stress Isolation and Method of Fabrication
PCT:
PCT/US2010/044517 ↗
Power Transistor with Turn Off Control and Method for Operating
PCT:
PCT/US2010/044544 ↗
Power Transistor Circuit
PCT:
PCT/US2010/044550 ↗
Operating an Emulated Electrically Erasable (Eee) Memory
PCT:
PCT/US2010/044557 ↗
Memory Device and Method
PCT:
PCT/US2010/045573 ↗
Semiconductor Device with Oxygen-Diffusion Barrier Layer and Method for Fabricating Same
PCT:
PCT/US2010/045582 ↗
Capacitive Touch Sensor Device Configuration Systems and Methods
PCT:
PCT/US2010/045583 ↗
Semiconductor Wafer Having Scribe Lane Alignment Marks for Reducing Crack Propagation
PCT:
PCT/US2010/049636 ↗
Memory Device and Method Thereof
PCT:
PCT/US2010/049958 ↗
One-Time Programmable Memory Device and Methods Thereof
PCT:
PCT/US2010/053205 ↗
Methods and Apparatus for Performing Capacitive Touch Sensing and Proximity Detection
PCT:
PCT/US2010/055263 ↗
Systems and Methods for Delivering Power in Response to a Connection Event
PCT:
PCT/US2010/055271 ↗
Micro Electromechanical Systems (Mems) Having a Gap Stop and Method Therefor
PCT:
PCT/US2010/057618 ↗
Electrical Coupling of Wafer Structures
PCT:
PCT/US2010/057624 ↗
Bond Pad with Multiple Layer Over Pad Metallization and Method of Formation
PCT:
PCT/US2010/059662 ↗
Method of Making a Semiconductor Structure Useful in Making a Split Gate Non-Volatile Memory Cell
PCT:
PCT/US2011/020029 ↗
Non-Volatile Memory Device and Method Therefor
PCT:
PCT/US2011/020349 ↗
Esd Protection Device and Method
PCT:
PCT/US2011/020358 ↗
Data Processing System Having Brown-Out Detection Circuit
PCT:
PCT/US2011/021709 ↗
Quiescent Current (Iddq) Indication and Testing Apparatus and Methods
PCT:
PCT/US2011/021711 ↗
Dc to Dc Converter Having Switch Control and Method of Operation
PCT:
PCT/US2011/023616 ↗
Semiconductor Device and Method of Fabricating Same
PCT:
PCT/US2011/023993 ↗
Apparatus and Method to Compensate for Injection Locking
PCT:
PCT/US2011/025872 ↗
Scheduling Memory Access Requests Using Predicted Memory Timing and State Information
PCT:
PCT/US2011/026632 ↗
Packaging Process to Create Wettable Lead Flank During Board Assembly
PCT:
PCT/US2011/027527 ↗
Multi-Port Memory Having a Variable Number of Used Write Ports
PCT:
PCT/US2011/030735 ↗
Open Circuit Detector and Method Therefore
PCT:
PCT/US2011/030745 ↗
Emulated Electrically Erasable (Eee) Memory and Method of Operation
PCT:
PCT/US2011/031084 ↗
Overvoltage Protection Circuit for an Integrated Circuit
PCT:
PCT/US2011/031183 ↗
Circuit for Verifying the Write Enable of a One Time Programmable Memory
PCT:
PCT/US2011/032739 ↗
Data Processor Having Multiple Low Power Modes
PCT:
PCT/US2011/033211 ↗
Transmission Gate Circuitry for High Voltage Terminal
PCT:
PCT/US2011/035727 ↗
Switching Regulator with Input Current Limiting Capabilities
PCT:
PCT/US2011/038319 ↗
Method for Manufacturing a Semiconductor Device and Semiconductor Device Obtainable with Such a Method
Power Management Arrangement for a Mobile Device
Method and System of Adaptive Predistortion of a Wireless Transmitter
Prolonging Internal Power Supply Life in a Mobile Communication Device
Method for Manufacturing a Non-Volatile Memory, Non-Volatile Memory Device, and an Integrated Circuit
Method, Integrated Circuit, and Communication Unit for Scheduling a Processing of Packet Stream Channels
Overcurrent Protection Circuit, Integrated Circuit, Apparatus and Computer Program Product
System and Method to Improve Switching in Power Switching Applications
Amplifier Circuit
Amplifier Circuit Audio Circuit and Electronic Device
Semiconductor Device and Apparatus Including Semiconductor Device
Semiconductor Device and Apparatus Including Semiconductor Device
Rf Power Transistor Circuit
Interlayer Dielectric Under Stress for an Integrated Circuit
Application:
12/752,699 →
Publication:
US 2010/0190354
Packaging Process to Create Wettable Lead Flank During Board Assembly
Lead Frame Having a Recess Structure for Reducing the Leadframe Delamination of Semiconductor Device.
Application:
12/753,118 →
Publication:
US 2010/0283135
Process for Forming an Electronic Device Including a Fin-Type Transistor Structure
Driver Circuit
Method and Circuit for Calibrating Data Capture in a Memory Controller
Multi-Port Memory Having a Variable Number of Used Write Ports
Method for Forming a Split Gate Device
Mimo Precoding Enabling Spatial Multiplexing, Power Allocation and Adaptive Modulation and Coding
Integrated Circuit Device with Reduced Leakage and Method Therefor
Monitor Circuit for Determining the Lifetime of a Semiconductor Device
Multiple Core Data Processor with Usage Monitoring
Application:
12/765,534 →
Publication:
US 2011/0265090
Back End of Line Metal-to-Metal Capacitor Structures and Related Fabrication Methods
Application:
12/765,575 →
Publication:
US 2011/0261500
Method for Forming a Schottky Diode Having a Metal-Semiconductor Schottky Contact
Programmable Delay Timer and Method Therefor
Ldmos Transistors with a Split Gate
Techniques for Updating Filter Coefficients of an Adaptive Filter
Open Circuit Detector and Method Therefore
Techniques for Implementing Adaptation Control of an Echo Canceller to Facilitate Detection of In-Band Signals
Data Processing System Having Peripheral-Paced Dma Transfer and Method Therefor
Switched Capacitor Circuit for a Voltage Controlled Oscillator
Ldmos with Enhanced Safe Operating Area (Soa) and Method Therefor
Multiple Partitioned Emulated Electrically Erasable (Eee) Memory and Method of Operation
Emulated Electrically Erasable (Eee) Memory and Method of Operation
Amplifier with Feedback
Patent:
7,986,189 →
Application:
12/770,463 →
Circuit for Verifying the Write Enable of a One Time Programmable Memory
Overvoltage Protection Circuit for an Integrated Circuit
Data Transfer Coherency Device and Methods Thereof
Method for Forming a Vertical Mos Transistor
Method for Synchronizing Remote Device
Battery Charging Circuit and Battery Charger
Battery Charging Circuit
Sensor Output Circuit
Resistor Testing Circuit and Battery Charger Including Resistor Testing Circuit
Application:
12/784,496 →
Publication:
US 2010/0315037
Integrated Circuit Using Finfets and Having a Static Random Access Memory (Sram)
Method and Apparatus for Displaying Video Data
Application:
12/786,460 →
Publication:
US 2011/0292292
System for Testing Integrated Circuit with Asynchronous Clock Domains
Duty Cycle Correction Circuit
Data Processor Having Multiple Low Power Modes
Angled Ion Implantation in a Semiconductor Device
Data Processing System Having an Operating System Adapter and Method
Method of Forming a Shared Contact in a Semiconductor Device
Method and System for Integrated Circuit Power Supply Management
Method for Supplying an Output Supply Voltage to a Power Gated Circuit and an Integrated Circuit
Video processing system, computer program product and method for managing a transfer of information between a memory unit and a decoder
Video processing system, computer program product and method for decoding an encoded video stream
Application:
12/788,394 →
Publication:
US 2011/0293019
Clock Simulation Device and Methods Thereof
Semiconductor Chip Grid Array Package and Method for Fabricating Same
Application:
12/790,999 →
Publication:
US 2011/0108967
Method of Making Routable Layout Pattern Using Congestion Table
High Voltage Deep Trench Capacitor
Methods and Apparatus for an Isfet
Method of Assembling Semiconductor Device with Heat Spreader
Patent:
8,012,799 →
Application:
12/795,664 →
Method and System for Generating Wavelets
Pilot Signal in an Fdma Communication System
Methods and apparatus for orthogonal modulated signals
Memory Mapping System, Request Controller, Multi-Processing Arrangement, Central Interrupt Request Controller, Apparatus, Method for Controlling Memory Access and Computer Program Product
Performance estimation for adjusting processor parameter to execute a task taking account of resource available task inactive period
Semiconductor Device and Differential Amplifier Circuit Therefor
Semiconductor Processing Method
Processor Based System Having Ecc Based Check and Access Validation Information Means
Mos Transistor Drain-to-Gate Leakage Protection Circuit and Method Therefor
Method and Apparatus for Regulating a Field Current for an Alternator Device
Contention Free Parallel Access System and a Method for Contention Free Parallel Access to a Group of Memory Banks
Method of Forming Openings in a Semiconductor Device and a Semiconductor Device Fabricated by the Method
Lead Frame Based, Over-Molded Semiconductor Package with Integrated Through Hole Technology (Tht) Heat Spreader Pin(S) and Associated Method of Manufacturing
Error Detection in a Content Addressable Memory (Cam) and Method of Operation
Methods of Making Laterally Double Diffused Metal Oxide Semiconductor Transistors Having a Reduced Surface Field Structure
Circuit Having Gate Drivers Having a Level Shifter
Switching Regulator with Input Current Limiting Capabilities
Method for Testing a Contact Structure
Refresh Operation During Low Power Mode Configuration
Transmission Gate Circuitry for High Voltage Terminal
Recovery Scheme for an Emulated Memory System
Integrated Circuit Module and Method of Packaging Same
Device Structures for in-Plane and Out-of-Plane Sensing Micro-Electro-Mechanical Systems (Mems)
Dynamic Pad Size to Reduce Solder Fatigue
Method of Forming Semiconductor Package
Method of Packaging Semiconductor Device
Application:
12/830,424 →
Publication:
US 2011/0165729
Dual Die Semiconductor Package
Differential Amplifier That Compensates for Process Variations
Patent:
8,035,448 →
Application:
12/832,295 →
System and Method to Control One Time Programmable Memory
Battery Cell Equalizer System
Current Reduction in a Single Stage Cyclic Analog to Digital Converter with Variable Resolution
Soft Program of a Non-Volatile Memory Block
Capacitor Device Using an Isolated Well and Method Therefor
Low Voltage Detector
Use of Multiple Internal Sensors for Measurement Validation
Method of Forming a Packaged Semiconductor Device
Guard Ring Integrated Ldmos
Integrated Circuit Having Low Power Mode Voltage Regulator
Application:
12/843,547 →
Publication:
US 2010/0283445
System and Method for Setting Counter Threshold Value
Rechargeable Device and Method for Determining Universal Serial Bus Port Type
Integrated Circuit Package with Voltage Distributor
Data Processing Having Multiple Low Power Modes and Method Therefor
Silicided Base Structure for High Frequency Transistors
Gain Enhanced Switched Capacitor Circuit and Method of Operation
Patent:
8,026,760 →
Application:
12/846,475 →
Analog-To-Digital Converter Having a Comparator for a Multi-Stage Sampling Circuit and Method Therefor
Method for Forming a Capped Micro-Electro-Mechanical System (Mems) Device
Patent:
8,039,312 →
Application:
12/847,465 →
Memory with Low Voltage Mode Operation
Electronic Circuit and Method for Operating a Module in a Functional Mode and in an Idle Mode
Data Procssing System with Peripheral Configuration Information Error Detection
Semiconductor Package and Method of Testing Same
Synchroniser Circuit and Method
Application:
12/852,513 →
Publication:
US 2012/0033772
Pulsed Flip-Flop Circuit
Patent:
8,063,685 →
Application:
12/852,514 →
Multistage Voltage Regulator Circuit
Monolithic Microwave Integrated Circuit
Systems and Methods for Determining Instruction Execution Error by Comparing an Operand of a Reference Instruction to a Result of a Subsequent Cross-Check Instruction
Data Processing System Having Selective Redundancy and Method Therefor
Partially Depleted Dielectric Resurf LDMOS
Mems Pressure Sensor Device and Method of Fabricating Same
Mems Sensor Device with Multi-Stimulus Sensing and Method of Fabricating Same
Voltage Regulator with an Emitter Follower Differential Amplifier
MEMORY MANAGEMENT and method for allocation using free-list
Buffer Module, Receiver, Device and Buffering Method Using Windows
Intermediate Product for a Multichannel Fet and Process for Obtaining an Intermediate Product
Method and Apparatus for Decoding Received Data Signals
Reducing Power Consumption in a Portable Electronic Device with a Luminescent Element
Application:
12/866,247 →
Publication:
US 2010/0315535
Sigma-Delta Modulator Apparatus and Method of Generating a Modulated Output Signal
Analog to Digital Converter with Amplifier
Mixer Circuit
Processor for Use as a Path Searcher of a Spread Spectrum Receiver and a Method of Operation of the Processor
Charge Pump Having Ramp Rate Control
Touch Sensor Controller for Driving a Touch Sensor Shield
Schmitt Trigger with Test Circuit and Method for Testing
Comparator Circuit with Hysteresis, Test Circuit, and Method for Testing
Digital Signal Voltage Level Shifter
Patterning a Gate Stack of a Non-Volatile Memory (Nvm) Using a Dummy Gate Stack
Patterning a Gate Stack of a Non-Volatile Memory (Nvm) with Simultaneous Etch in Non-Nvm Area
Switched Varactor Circuit for a Voltage Controlled Oscillator
Result Forwarding to Dependent Instruction in Pipelined Processor with Mode Selectable Execution in E1 or E2 Pipelined Operational Stages
Mems Device Assembly and Method of Packaging Same
Bond Pad for Semiconductor Die
Semiconductor Package with Protective Tape
3-D Semiconductor Die Structure with Containing Feature and Method
Data Processing System Having End-to-End Error Correction and Method Therefor
Phase Change Memory Structures
Laterally Diffused Metal Oxide Semiconductor Device
Process of Forming an Electronic Device Including Insulating Layers Having Different Strains
Static Random Access Memory (Sram) Having Bit Cells Accessible by Separate Read and Write Paths
Integrated circuits with edge-adjacent devices having reactance values
Data Processor for Processing Decorated Instructions with Cache Bypass
Lateral Capacitor and Method of Making
Non-Volatile Memory (Nvm) with Imminent Error Prediction
System and Method for Descrambling Data
Master-Slave Flip-Flop with Timing Error Correction
Polymer Core Wire
Application:
12/889,428 →
Publication:
US 2012/0073859
Channel Rank Updates in Multiple-Input Multiple-Output Communication Systems
Semiconductor Device with Exposed Pad
Application:
12/891,820 →
Publication:
US 2012/0074549
Semiconductor Structure Having a Through Substrate via (Tsv) and Method for Forming
Digital Audio Processing System and Method
Generalized Reference Signaling Scheme for Multi-User, Multiple Input, Multiple Output (Mu-Mimo) Using Arbitrarily Precoded Reference Signals
Electronic Device Including Interconnects with a Cavity Therebetween and a Process of Forming the Same
Switched Mode Voltage Regulator and Method of Operation
Dual Port Static Random Access Memory Cell Layout
Method for Compensating for Variations in Data Timing
Process of Forming an Electronic Device Including a Conductive Stud Over a Bonding Pad Region
Semiconductor Devices with Enclosed Void Cavities
Mos Capacitor Structures
Rom Memory Device
Bipolar Transistor with Improved Stability
Split Gate Non-Volatile Memory Cell with Improved Endurance and Method Therefor
Efficient Replaying of Autograded Coverage Regressions and Performance Verification with Directed Testcases
Bipolar Transistors Having Emitter-Base Junctions of Varying Depths and/or Doping Concentrations
Apparatus and Method for Decoupling Asynchronous Clock Domains
Brown-Out Detection Circuit
Eutectic Flow Containment in a Semiconductor Fabrication Process
Method of Producing Layered Wafer Structure Having Anti-Stiction Bumps
Application:
12/914,908 →
Publication:
US 2012/0107992
Data Processing System Having Selective Invalidation of Snoop Requests and Method Therefor
Non-Volatile Memory and Logic Circuit Process Integration
Directional Couplers for Use in Electronic Devices, and Methods of Use Thereof
Method of Making a Micro-Electro-Mechanical-Systems (Mems) Device
Debugger Recovery on Exit from Low Power Mode
Power Detector
Application:
12/918,168 →
Publication:
US 2010/0330938
Dtmf Tone Monitoring Apparatus and Method of Identifying a Dtmf Tone
Dc Compensation for Vlif Signals
Method for Protecting a Cryptographic Module and a Device Having Cryptographic Module Protection Capabilities
Latch Module and Frequency Divider
Apparatus and a Method for Detecting Faults in the Delivery of Electrical Power to Electrical Loads
Clock Signal Generating Arrangement for a Communication Device
Poly-Resistor, and Linear Amplifier
Microprocessor Having a Low-Power Mode and a Non-Low Power Mode, Data Processing System and Computer Program Product
Device and Method for Evaluating Connectivity Between a Video Driver and a Display
System and a Method for Selecting a Cache Way
Surface Treatment in Semiconductor Manufacturing
Microcontroller Device, Microcontroller Debugging Device, Method of Debugging a Microcontroller Device, Microcontroller Kit
Method of Sealing an Air Gap in a Layer of a Semiconductor Structure and Semiconductor Structure
Pll System and Method for Controlling a Gain of a Vco Circuit
Wireless Communication Unit and Semiconductor Device Having a Power Amplifier Therefor
Multiplexing and Demultiplexing Data
Voltage-Controlled Oscillator and Radar System
Oscillator Circuit
Synchronization of Stateful Elements in a Processing Resource Using a Scan Chain
Semiconductor Device Having Die Pads Isolated from Interconnect Portion and Method of Assembling Same
Electronic Circuit and Method for Operating a Circuit in a Standby Mode and in an Operational Mode
Application:
12/938,493 →
Publication:
US 2012/0105125
Non-Volatile Memory (Nvm) Erase Operation with Brownout Recovery Technique
Method for Programming a Multi-State Non-Volatile Memory (Nvm)
Area-Efficient High Voltage Bipolar-Based ESD Protection Targeting Narrow Design Windows
Decimation Filter
Integrated antenna package
Radar Module
Differential Equalizers with Source Degeneration and Feedback Circuits
Pressure Transducer Having Structure for Monitoring Surface Charge
Integrated Non-Volatile Memory (Nvm) and Method Therefor
Method and Apparatus for Eeprom Emulation for Preventing Data Loss in the Event of a Flash Block Failure
Pll Start-Up Circuit
Surface Mount Semiconductor Device
System and Method for Scan Testing Integrated Circuits
Application:
12/954,907 →
Publication:
US 2012/0137187
Die Temperature Sensor Circuit
Automotive Radar System and Method for Using Same
Esd Protection with Increased Current Capability
Semiconductor Package with Pre-Formed Ball Bonds
Application:
12/957,419 →
Publication:
US 2011/0068469
Pressure Sensor and Method of Assembling Same
Shielding Structures for Signal Paths in Electronic Devices
Nanocrystal Memory with Differential Energy Bands and Method of Formation
Scan Based Test Architecture and Method
Dielectric Layer for Gallium Nitride Transistor
Application:
12/971,165 →
Publication:
US 2012/0156843
Coherency Groups of Serially Coupled Processing Cores Propagating Coherency Information Containing Write Packet to Memory
Multi-Gate Semiconductor Devices
Channel Sounding Techniques for a Wireless Communication System
Cache Result Register for Quick Cache Information Lookup
Exponential Charge Pump
Multiple Sensor Thermal Management for Electronic Devices
Read Conditions for a Non-Volatile Memory (Nvm)
Method for Forming an Over Pad Metalization (Opm) on a Bond Pad
Application:
12/985,906 →
Publication:
US 2012/0178189
Method and Apparatus for Control of an Ac Electric Motor with Field Weakening
Method for Sampling Data and Apparatus Therefor
Method and Apparatus for Detecting a Set Up Signal Used for Data Communication Over a Communication Network
Method and Apparatus for Interleaving a Data Stream Using Quadrature Permutation Polynomial Functions (Qpp)
Display Controller, Image Processing System, Display System, Apparatus and Computer Program Product
Semiconductor Device and Method for Validating a State Thereof
Temperature Compensation Circuit and Method for Generating a Voltage Reference with a Well-Defined Temperature Behavior
Electrostatic Discharge Protection Circuit, Equipment and Method
Method and Apparatus for Enabling Communication Between a First Device and at Least One Further Device
System, Method and Program Product for Determining Execution Flow of the Scheduler in Response to Setting a Scheduler Control Variable by the Debugger or by a Processing Entity
System, Method and Computer Program Product for Scheduling a Processing Entity Task by a Scheduler in Response to a Peripheral Task Completion Indicator
System, and Computer Program Product for Scheduling Processor Entity Tasks in a Multiple-Processing Entity System
Application:
12/994,033 →
Publication:
US 2011/0099552
Memory System with Redundant Data Storage and Error Correction
System for Dynamically Distributing an Available Memory Resource to Redundant and Non-Redundant Storage Areas Using Ram Routing Logic
Semiconductor Device and Method of Electrostatic Discharge Protection Therefor
Patching of a Read-Only Memory
Application:
12/997,087 →
Publication:
US 2011/0107070
Channel Condition Dependent Scheduling
Voltage Controlled Oscillator (Vco) Circuit with Integrated Compensation of Thermally Caused Frequency Drift
Method and Apparatus for Generating a Modulated Waveform Signal
Multi-Frequency Tone Detector
Fault Management for a Communication Bus
Processing Position-Related Input Data from a Rotational Machine Whose Angular Speed Is Variable
Method of Forming a Power Semiconductor Device and Power Semiconductor Device
Method and Apparatus for Detecting One or More Predetermined Tones Transmitted Over a Communication Network
Fault Detection Apparatus for Alphanumeric Display System and Method of Detecting a Fault
Application:
13/003,948 →
Publication:
US 2011/0109602
Semiconductor Device, Wireless Communication Device and Method for Generating a Synthesized Frequency Signal
Method of Making Semiconductor Package with Improved Standoff
Method for Making Semiconductor Package
Lead Frame for Semiconductor Die
Application:
13/004,031 →
Publication:
US 2011/0193207
Digital Phase Locked Loop with Reduced Switching Noise
Ldo Linear Regulator with Improved Transient Response
Power Switch for Decreased Ramp Rate
Cmos Device Structures
Amplifiers and Related Receiver Systems
Methods of Making Multi-State Non-Volatile Memory Cells
Methods of Forming Semiconductor Devices Having Conductors with Different Dimensions
Device Having Conductive Substrate via with Catch-Pad Etch-Stop
Switched-Capacitor Programmable-Gain Amplifier
Lead Frame Sheet
Method of Testing Asynchronous Modules in Semiconductor Device
Mems Sensor with Folded Torsion Springs
Mems Sensor with Dual Proof Masses
Voltage Regulation Circuitry and Related Operating Methods
Program Trace Message Generation for Page Crossing Events for Debug
Method and Apparatus for Processing Temporal and Spatial Overlapping Updates for an Electronic Display
Bipolar Transistor with Two Different Emitter Portions Having Same Type Dopant of Different Concentrations for Improved Gain
Multiple Function Power Domain Level Shifter
Selective Cache Access Control Apparatus and Method Thereof
Memory Having a Latching Sense Amplifier Resistant to Negative Bias Temperature Instability and Method Therefor
Selective Memory Access to Different Local Memory Ports and Method Thereof
Programming a Non-Volatile Memory
In-Line Register File Bitcell
Low Power, High Resolution Timing Generator for Ultra-Wide Bandwidth Communication Systems
Lead Frame with Recessed Die Bond Area
Application:
13/018,438 →
Publication:
US 2011/0241187
Electronic Circuit Having Shared Leakage Current Reduction Circuits
Method for Reducing Surface Area of Pad Limited Semiconductor Die Layout
Estimation and Compensation of Clock Variation in Received Signal
Lead Frame for Semiconductor Device
Erase Ramp Pulse Width Control for Non-Volatile Memory
Bipolar Transistor and Method with Recessed Base Electrode
Method and System for Detecting Retransmission Threshold Condition in Selective Repeat Arq Communication System
Method of Assembling Semiconductor Devices Including Saw Singulation
Application:
13/025,143 →
Publication:
US 2011/0263077
Phase-Shifted Pulse Width Modulation Signal Generation Device and Method Therefor
Near Zero Channel Length Field Drift Ldmos
Digital Method to Obtain the I-V Curves of Nvm Bitcells
System and Method to Control One Time Programmable Memory
Mems Device Having Variable Gap Width and Method of Manufacture
Anchored Conductive via and Method for Forming
System on a Chip with Clock Circuits
Application:
13/030,411 →
Publication:
US 2011/0145623
Accelerometer and Automatic Calibration of Same
Application:
13/031,545 →
Publication:
US 2012/0215477
Magnetometer Test Arrangement and Method
Memory Protection in a Data Processing System
Application:
13/033,317 →
Publication:
US 2012/0215989
Remote Permissions Provisioning for Storage in a Cache and Device Therefor
MEMS Device With Enhanced Resistance to Stiction
Semiconductor Devices Having Reduced Gate-Drain Capacitance
Varactor Diodes
Microprocessor Systems and Methods for Latency Tolerance Execution
Systems and Methods for Reconfiguring Cache Memory
Vias Between Conductive Layers to Improve Reliability
Non-Volatile Memory (Nvm) Cell for Endurance and Method of Making
Multiple Patterning Consistency Processing
Application:
13/036,604 →
Publication:
US 2012/0219917
Systems and Methods for Configuring Load/Store Execution Units
Multilayered Through a Via
Read Stacking for Data Processor Interface
Method to Form a Via
Bipolar Transistors with Hump Regions
Semiconductor Devices with Low Leakage Schottky Contacts
Systems and Methods for Detecting Surface Charge
Methods for Forming Through-Substrate Conductor Filled Vias, and Electronic Assemblies Formed Using Such Methods
Layout Method for Integrated Circuit Including Vias
Application:
13/044,578 →
Publication:
US 2012/0233575
Memory Voltage Regulator with Leakage Current Voltage Control
Hierarchical Error Correction for Large Memories
Adaptive Bandwidth Phase-Locked Loop
Method of Re-Ordering Received Data Blocks in Hybrid Automatic Repeat Request Telecommunication System
Method for Detecting Audio Signal Transient and Time-Scale Modification Based on Same
Stepper Motor Controller and Method for Controlling Same
Lead Frame for Semiconductor Package
Switched-Capacitor Amplifier Circuit
Patent:
8,198,937 →
Application:
13/048,113 →
A Transistor Having Gate Dielectric Protection and Structure
Synchronous Data Processing System for Reliable Transfer of Data Irrespective of Propagation Delays and Process, Voltage and Temperature (Pvt) Variations
Memory Controller Address and Data Pin Multiplexing
Voltage-Controlled Oscillators and Related Systems
Split-Gate Non-Volatile Memory Cell Having Improved Overlap Tolerance and Method Therefor
Patent:
8,163,615 →
Application:
13/052,529 →
Programmable Temperature Sensing Circuit for an Integrated Circuit
Selective Checkbit Modification for Error Correction
Integrated Circuit Die, an Integrated Circuit Package and a Method for Connecting an Integrated Circuit Die to an External Device
System for Monitoring and Controlling the Power of a Radio Frequency (Rf) Signal in a Short-Range Rf Transmitter
Micro Controller Unit Including an Error Indicator Module
Integrated Testing Circuitry for High-Frequency Receiver Integrated Circuits
Heterodyne Receiver
Semiconductor Device Wireless Communication Unit and Method for Receiving a Signal
Application:
13/055,480 →
Publication:
US 2011/0116577
Communications Module Apparatus, Integrated Circuit and Method of Communicating Data
Die Temperature Estimator
Buffer Apparatus, Integrated Circuit and Method of Reducing a Portion of an Oscillation of an Output Signal
Security Key Generator
Wireless Communication Unit, Integrated Circuit and Method of Power Control of a Power Amplifier Therefor
Voltage Regulator with Low and High Power Modes
System and Method for Communicating on an Electrical Bus
Semiconductor Device, Wireless Communication Device and Method for Generating a Synthesized Frequency Signal
Multi-Core Clocking System with Interlocked 'Anti-Freeze' Mechanism
Calibration Apparatus and Method of Calibrating a Communications Terminal
Computational Generation of Narrow-Bandwidth Digital Signals
Wireless Communication Unit, Semiconductor Device and Power Control Method Therefor
Method and Apparatus for Transmitting Data
Method and Apparatus for Transmitting Data
Wireless Communication Unit, Integrated Circuit and Method of Power Control of a Power Amplifier Therefor
Method and Apparatus for Gating a Clock Signal
Method for Adjusting Time Slots in a Communication Network
Wake-Up Control System and Method for Controlling Receiver Wake-Up
Electrostatic Occupant Detection System
Low-Leakage, High-Capacitance Capacitor Structures and Method of Making
Selectable Threshold Reset Circuit
System and Method for Debugging Scan Chains
Dual Loop Phase Locked Loop with Low Voltage-Controlled Oscillator Gain
Circuit for Preventing a Dummy Read in a Memory
Correlated-Double-Sampling Switched-Capacitor Gain Stages, Systems Implementing the Gain Stages, and Methods of Their Operation
Correlated-Level-Shifting and Correlated-Double-Sampling Switched-Capacitor Gain Stages, Systems Implementing the Gain Stages, and Methods of Their Operation
Method for Reducing Plasma Discharge Damage During Processing
Non-Volatile Memory and Logic Circuit Process Integration
Non-Volatile Memory and Logic Circuit Process Integration
Patterning a Gate Stack of a Non-Volatile Memory (Nvm) with Formation of a Capacitor
Patterning a Gate Stack of a Non-Volatile Memory (Nvm) with Formation of a Metal-Oxide-Semiconductor Field Effect Transistor (Mosfet)
Patterning a Gate Stack of a Non-Volatile Memory (Nvm) with Formation of a Gate Edge Diode
Method and System to Compensate for Temperature and Pressure in Piezo Resistive Devices
Common Rf Interface for Separating and Mixing Wireless Signals
Method and Apparatus for Self-Test of Successive Approximation Register (Sar) a/D Converter
Memory Controller and Method for Accessing a Plurality of Non-Volatile Memory Arrays
Resistive Random Access Memory (Ram) Cell and Method for Forming
Application:
13/085,208 →
Publication:
US 2012/0261635
Resistive Random Access Memory (Ram) Cell and Method for Forming
Method for Forming a Semiconductor Device Having Nanocrystal
Method for Forming a Semiconductor Device Having Nanocrystals
Method of Making a Semiconductor Structure Useful in Making a Split Gate Non-Volatile Memory Cell
Power Mosfet with a Gate Structure of Different Material
Method for Etched Cavity Devices
Etching Trenches in a Substrate
Mems Device with Central Anchor for Stress Isolation
Dynamic Lockstep Cache Memory Replacement Logic
Cache Memory with Dynamic Lockstep Support
Sensor Device with Sealing Structure
Methods for Fabricating Sensor Device Package Using a Sealing Structure
Isolated Capacitors Within Shallow Trench Isolation
Decoupling Capacitors Recessed in Shallow Trench Isolation
Thin Semiconductor Package and Method for Manufacturing Same
Method of Assembling Shielded Integrated Circuit Device
Method and Apparatus for Dc-to-Dc Conversion
Application:
13/092,164 →
Publication:
US 2011/0316511
Method and System for Touch Sensor Interface Fault Detection
Semiconductor Device with Nested Rows of Contacts
Patent:
8,080,448 →
Application:
13/092,170 →
Digital Audio Processing System and Method
Dynamic Programming for Flash Memory
System for Performing Electrical Characterization of Asynchronous Integrated Circuit Interfaces
A Register Renaming Scheme with Checkpoint Repair in a Processing Device
High Pressure Deuterium Treatment for Semiconductor/High-K Insulator Interface
Mixer Circuits for Second Order Intercept Point Calibration
Method for Protecting Copper Wire Bonds on Aluminum Pads of a Semiconductor Device from Corrosion.
Method and Apparatus for Integrated Circuit Packages Using Materials with Low Melting Point
Patent:
8,252,631 →
Application:
13/096,269 →
Microprocessor Systems and Methods for a Combined Register File and Checkpoint Repair Register
Load Control and Protection System
Method of Making a Semiconductor Device as a Capacitor
Semiconductor Device Structure as a Capacitor
Dc Offset Calibration in a Direct Conversion Receiver
Flip-Flop Circuit with Internal Level Shifter
Mold and Substrate for Use with Mold
Voltage Regulator with Different Inverting Gain Stages
Selective Error Detection and Error Correction for a Memory Interface
Mems Device with Impacting Structure for Enhanced Resistance to Stiction
Electrically Programmable Fuse Module in Semiconductor Device
Selective Routing of Local Memory Accesses and Device Thereof
Phase Locked Loop Circuit Having a Voltage Controlled Oscillator with Improved Bandwidth
Object Detection Device with Variable Sensitivity Electric Field Measurement Circuit
Transistors with Immersed Contacts
System and Method for Scalable Movement and Replication of Data
Audio Source System and Method
Charge Pump for Phase Locked Loop
Memory with Discrete Storage Elements
Method of Forming a Semiconductor Device Featuring a Gate Stressor and Semiconductor Device
Charge Pump Circuit with Fast Start-Up
Methods and Apparatus to Improve Reliability of Isolated Vias
Audio Output Driver for Reducing Electromagnetic Interference and Improving Audio Channel Performance
Microprocessor Systems and Methods for Handling Instructions with Multiple Dependencies
Method for Forming an Asymmetric Semiconductor Device
Application:
13/117,191 →
Publication:
US 2012/0302022
Semiconductor Sensor Device and Method of Packaging Same
Application:
13/118,596 →
Publication:
US 2012/0306031
Flexible Bus Driver
Processing Load with Normal or Fast Operation Mode
Wireless Communication Unit, Integrated Circuit and Method of Power Control of a Power Amplifier Therefor
Wireless Communication Device and Semiconductor Package Device Having a Power Amplifier Therefor
Method and Apparatus for Handling an Output Mismatch
Bus Driver for Avoiding an Overvoltage
Temperature Compensation in a Phase-Locked Loop
Application:
13/121,693 →
Publication:
US 2011/0260761
Semiconductor Device and Electronic Device
Complementary Band-Gap Voltage Reference Circuit
Integrated Circuit, Communication Unit and Method for Phase Compensation
Method for Singulating Electronic Components from a Substrate
Multimode Voltage Regulator and Method for Providing a Multimode Voltage Regulator Output Voltage and an Output Current to a Load
Method and Apparatus for Generating a Clock Signal
Frequency Multiplier Circuit
Logic Built-in Self-Test System and Method for Applying a Logic Built-in Self-Test to a Device Under Test
Resource Allocation Within Multiple Resource Providers Based on the Incoming Resource Request and the Expected State Transition of the Resource Requesting Application, and Selecting a Resource Provider Based on the Sum of the Percentage of the Resource Provider Cu
Electromechanical Transducer Device and Method of Forming a Electromechanical Transducer Device
Electromechanical Transducer Device and Method of Forming a Electromechanical Transducer Device
Allocation of Communication Channels
Operating Parameter Control for a Power Amplifier
Power Mos Transistor Device and Switch Apparatus Comprising the Same
Power Mos Transistor Device
Compiler Optimisation Like Idiom Recognition Through Pattern Matching Using Value Numbering
High Power Semiconductor Device for Wireless Applications and Method of Forming a High Power Semiconductor Device
Current Sensing Circuitry and Integrated Circuit and Method for Sensing a Current
Amplifier Circuitry, Integrated Circuit and Communication Unit
Clock Glitch Detection Circuit
Circuit and Method for Speed Monitoring of an Electric Motor
Method, System and Integrated Circuit for Enabling Access to a Memory Element
Determining Initial Rotor Position of an Alternating Current Motor
System and Method for Efficient Image Feature Extraction
Integrated Circuit Comprising Deflicker Unit for Filtering Image Data, and a Method Therefor
Capacitance Sensing Circuit and Method of Capacitance Sensing
Oscillator Circuit
Microprocessor Architecture and Method of Instruction Decoding with Partial Operation Code (Opcode) Suppression
Application:
13/142,431 →
Publication:
US 2011/0271083
Package Assembly and Method of Tuning a Natural Resonant Frequency of a Package
Semiconductor Structure, an Integrated Circuit Including a Semiconductor Structure and a Method for Manufacturing a Semiconductor Structure
Processing Data Flows
Priority Search Trees
Logarithmic Detector and Method of Pre-Charging an Average Filter on a Logarithmic Detector
Integrated Circuit Comprising Frequency Generation Circuitry for Controlling a Frequency Source
Integrated Circuit Comprising Frequency Generation Circuitry for Controlling a Frequency Source
Clock Glitch Detection
Control of Interrupt Generation for Cache
Cache Locking Control
Double Edge Triggered Flip Flop
Schottky Diodes
Active Tiling Placement for Improved Latch-Up Immunity
Dual Port Pressure Sensor
Method of Making a Dual Port Pressure Sensor
Method of Providing an Electronic Device Including Dies, a Dielectric Layer, and an Encapsulating Layer
Systems and Methods for Tracking Intellectual Property
Method and System for Address Conflict Resolution
Writing Data to System Memory in a Data Processing System in Which Cache Line States Are Tracked
Relaxation Oscillator with Low Power Consumption
System and Method for Generating Round Keys
Application:
13/159,443 →
Publication:
US 2012/0321079
High Efficiency Amplifier with Reduced Parasitic Capacitance
Selective Masking for Error Correction
Semiconductor Device with a Controlled Cavity and Method of Formation
Vented Substrate for Semiconductor Device
Heater Block for Wire Bonding System
Application:
13/160,522 →
Publication:
US 2012/0318853
Circuit and Method for Determining Comparator Offsets of Electronic Devices
Low Voltage Detector
Branch Target Buffer Addressing in a Data Processor
Voltage Controlled Oscillator Having a Resonator Circuit with a Phase Noise Filter
Application:
13/163,036 →
Publication:
US 2012/0319787
Method and Apparatus for Snoop-and-Learn Intelligence in Data Plane
Stacked and Shielded Packages with Interconnects
Application:
13/165,371 →
Publication:
US 2011/0250721
Recovery Method for Poor Yield at Integrated Circuit Die Panelization
Method for Forming a Semiconductor Device Having a Cobalt Silicide
Application:
13/166,561 →
Publication:
US 2012/0329234
Bandwidth Control for a Direct Memory Access Unit Within a Data Processing System
Word Line Fault Detection
Dynamic Random Access Memory (Dram) Refresh
Using Built-in Self Test for Preventing Side Channel Security Attacks on Multi-Processor Systems
Adaptive Write Procedures for Non-Volatile Memory Using Verify Read
Adaptive Write Procedures for Non-Volatile Memory
Leadframe for Semiconductor Device
Brace for Wire Bond
System on a Chip with Interleaved Sets of Pads
Data Processing System Having a Sequence Processing Unit and Method of Operation
Data Processing System Having a Sequence Processing Unit and Method of Operation
Application:
13/170,289 →
Publication:
US 2013/0007533
Method for Forming a Toroidal Inductor in a Semiconductor Substrate
High Speed Overlay Mode for Burst Data and Real Time Streaming (Audio) Applications
Electronic Elements and Devices with Trench Under Bond Pad Feature
Lead Frame Based Semiconductor Package and a Method of Manufacturing the Same
Integrated Assist Features for Epitaxial Growth
Apparatus and Methods for Quad Flat No Lead Packaging
Systems and Methods for Memory Region Descriptor Attribute Override
Comparator
Systems and Methods for Data Conversion
Systems and Methods for Data Conversion
Through Substrate Vias
Method of Testing Digital-to-Analog and Analog-to-Digital Converters
Fused Buss for Plating Features on a Semiconductor Die
Fused Buss for Plating Features on a Semiconductor Die
Method for Partitioning Scan Chain
Power Supply and Data Signal Interface Circuit with Overvoltage Protection
Method of Making a Die with Recessed Alumium Die Pads
Combined Output Buffer and ESD Diode Device
Oscillator Systems Having Annular Resonant Circuitry
Bonded Wire Semiconductor Device
Code Coverage Circuitry
Data Processing with Variable Operand Size
Semiconductor Device with Appraisal Circuitry
Integrated Protection Circuit
Method and Apparatus for Selecting at Least One Device to Be Wirelessly Controlled
Semiconductor Package with a Heat Spreader and Method of Making
Application:
13/205,228 →
Publication:
US 2013/0037931
Semiconductor Devices with Low Resistance Back-Side Coupling
Configurable Continuous Time Sigma Delta Analog-to-Digital Converter
Method and Device for Controlling Debug Event Resources
Brace for Long Bond Wire
Semiconductor Device with Nested Rows of Contacts
Application:
13/210,393 →
Publication:
US 2012/0112333
Attaching a Mems to a Bonding Wafer
Systems and Methods for Handling Instructions of in-Order and Out-of-Order Execution Queues
Systems and Methods for Handling Instructions of in-Order and Out-of-Order Execution Queues
Memory Device and Method Using Encode Values for Access Error Condition Detection
Data Processing System Operable in Single and Multi-Thread Modes and Having Multiple Caches and Method of Operation
Memory Management Unit Tag Memory with CAM Evaluate Signal
Memory Management Unit Tag Memory
Implant for Performance Enhancement of Selected Transistors in an Integrated Circuit
Semiconductor Device with Wake-Up Unit
Circuit Simulation Acceleration Using Model Caching
Method and System for Physical Verification Using Network Segment Current
Angular Rate Sensor with Different Gap Sizes
Application:
13/219,071 →
Publication:
US 2013/0047726
Integrated Circuit Having Critical Path Voltage Scaling and Method Therefor
Multi-Threading Flip-Flop Circuit
Back Side Alignment Structure and Manufacturing Method for Three-Dimensional Semiconductor Device Packages
Lead Frame Having a Flag with in-Plane and Out-of-Plane Mold Locking Features
Methods for Forming Antifuses with Curved Breakdown Regions
Semiconductor Device Packaging Having Pre-Encapsulation Through via Formation Using Drop-in Signal Conduits
Semiconductor Device Packaging Having Pre-Encapsulation Through via Formation Using Lead Frames with Attached Signal Conduits
Semiconductor Device Packaging Having Pre-Encapsulation Through via Formation
Application:
13/222,150 →
Publication:
US 2013/0049218
Mofset Mismatch Characterization Circuit
Mofset Mismatch Characterization Circuit
Process of Forming an Electronic Device Including a Resistor-Capacitor Filter
Contact for a Non-Volatile Memory and Method Therefor
Dual Port Static Random Access Memory Cell
Capacitive Sensor Radiation Measurement
Incident Capacitive Sensor
Integrated Circuit Having a Standard Cell and Method for Forming
Memory Management Unit (Mmu) Having Region Descriptor Globalization Controls and Method of Operation
Level Shifter Circuit
Efficient Word Lines, Bit Line and Precharge Tracking in Self-Timed Memory Device
Semiconductor Devices with Extended Active Regions
Application:
13/235,580 →
Publication:
US 2012/0007155
Low Power Cycle Data Converter
Layout Technique for Stress Management Cells
Phase Change Memory Cell with Heater and Method Therefor
Electrostatic Discharge Protection Circuit for an Integrated Circuit
Multi-Processor Data Processing System Having Synchronized Exit from Debug Mode and Method Therefor
Method of Reducing Power Leakage of Integrated Circuit
Application:
13/245,888 →
Publication:
US 2013/0080990
Adaptive IIP2 Calibration
Pressure Sensor and Method of Packaging Same
Application:
13/246,877 →
Publication:
US 2012/0139067
Method for Packaging an Electronic Device Assembly Having a Capped Device Interconnect
Interface System and Method with Backward Compatibility
Split Gate Memory Device with Gap Spacer
Application:
13/248,549 →
Publication:
US 2013/0084697
Method and Apparatus for Calculating Sensor Modelling Coefficients
Method and Circuit for Calculating Sensor Modelling Coefficients
Memory Protection Unit (Mpu) Having a Shared Portion and Method of Operation
Methods and Apparatus for Testing Multiple-Ic Devices
Methods for Forming Varactor Diodes
Voltage-Controlled Oscillators and Related Systems
Receiving Node in a Packet Communications System and Method for Managing a Buffer in a Receiving Node in a Packet Communications System
Radio Frequency Remote Controller Device, Integrated Circuit and Method for Selecting at Least One Device to Be Controlled
Connection Quality Verification for Integrated Circuit Test
System for Tree Sequence Testing of a Device and Method for Tree Sequence Testing of a Device in a Test Framework Architecture
Method and System Arranged for Filtering an Image
Wireless Communication Device and Semiconductor Package Device Having a Power Amplifier Therefor
Tone Relay System and Method
Apparatus, Communications System and Method for Optimizing Data Packet Flow
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Agreement
Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
Change of Name
Apr 16, 2014
From: LAGHA, ANISSA; FOX, ROBERT; BROUSSOUS, LUCILLE; LEVY, DIDIER
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032690/0835 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
Assignment and Assumption of Security Interest in Patents
Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
Assignment and Assumption of Security Interest in Patents
Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
Security Agreement Supplement
Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
Supplement to the Security Agreement
Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
Corrective Assignment to Correct the Remove Application 12092129 Previously Recorded on Reel 038017 Frame 0058. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
Release of Security Interest
Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
Release of Security Interest
Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
Change of Name
Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
Change of Name
Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
Merger
Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
Corrective Assignment to Correct the Nature of Conveyance Listed Change of Name Should Be Merger and Change Previously Recorded at Reel: 040652 Frame: 0180. Assignor(S) Hereby Confirms the Merger and Change of Name.
Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
Corrective Assignment to Correct the Remove Patents 8108266 and 8062324 and Replace Them with 6108266 and 8060324 Previously Recorded on Reel 037518 Frame 0292. Assignor(S) Hereby Confirms the Assignment and Assumption of Security Interest in Patents.
Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
Corrective Assignment to Correct the Remove Application 12681366 Previously Recorded on Reel 038017 Frame 0058. Assignor(S) Hereby Confirms the Security Agreement Supplement.
May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
Corrective Assignment to Correct the Remove Application 12681366 Previously Recorded on Reel 039361 Frame 0212. Assignor(S) Hereby Confirms the Security Agreement Supplement.
May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
Corrective Assignment to Correct the Nature of Conveyance Previously Recorded at Reel: 040632 Frame: 0001. Assignor(S) Hereby Confirms the Merger and Change of Name.
Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
Corrective Assignment to Correct the to Correct the Application No. from 13,883,290 to 13,833,290 Previously Recorded on Reel 041703 Frame 0536. Assignor(S) Hereby Confirms the the Assignment and Assumption of Security Interest in Patents..
Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
Release of Security Interest
Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
Release of Security Interest
Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 042985 Frame 0001. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 039361 Frame 0212. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 042762 Frame 0145. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →