IP Library Granted Patent US 8,436,582
Granted Patent B2
US 8,436,582 · App. 12/833,430 · Granted May 7, 2013

Battery cell equalizer system

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Quick Facts
Patent No.
US 8,436,582
App. No.
12/833,430
Granted
May 7, 2013
Kind
B2
Abstract

A method of operating a battery system includes a plurality of battery cells coupled in series. The plurality of cells includes at least three battery cells coupled in series. The method includes determining a cell with the greatest charge excess of the plurality of battery cells. The method further includes determining a cell with the greatest charge deficit of the plurality of battery cells. The method further includes discharging the cell with the greatest charge excess to charge, with a voltage converter, the cell with the greatest charge deficit.

Claims (46)

1. A method of operating a battery system comprising a plurality of battery cells coupled in series and a plurality of converter stages, wherein the plurality of battery cells includes at least three battery cells coupled in series and each converter stage of the plurality of converter stages is associated with a cell of the plurality of battery cells, the method comprising:

determining a cell with a greatest charge excess of the plurality of battery cells;

determining a cell with a greatest charge deficit of the plurality of battery cells;

discharging the cell with the greatest charge excess in order to charge, with a voltage converter, the cell with the greatest charge deficit, wherein the discharging comprises

using a converter stage associated with the cell with the greatest charge excess as a source stage of the voltage converter, and

using a converter stage associated with the cell with the greatest charge deficit as a sink stage of the voltage converter.

2. The method of claim 1 wherein the voltage converter is characterized as a SEPIC voltage converter.

3. The method of claim 1 further comprising:

after the discharging, determining a second cell with the greatest charge deficit of the plurality of battery cells; and

after the determining the second cell, discharging the cell with the greatest charge excess in order to charge, with a voltage converter, the second cell, wherein the discharging after the determining the second cell comprises

using the converter stage associated with the cell with the greatest charge excess as a source stage of the voltage converter, and

using a converter stage associated with the second cell as a sink stage of the voltage converter.

4. The method of claim 3 wherein:

during the discharging the cell, configuring the converter stage associated with the second cell in a passive configuration; and

during the discharging after determining the second cell, configuring the converter stage used as a sink stage for the discharging in a passive configuration.

5. The method of claim 1 further comprising:

after the discharging, determining a second cell with the greatest charge excess of the plurality of battery cells; and

after the determining the second cell, discharging the second cell in order to charge, with a voltage converter, the cell with the greatest charge deficit, wherein the discharging the second cell comprises using a converter stage of the second cell as a source stage of the voltage converter, and

using the converter stage of the cell associated with the greatest charge deficit as the sink stage of the voltage converter.

6. The method of claim 1 further comprising:

after the discharging, determining a second cell with the greatest charge deficit of the plurality of battery cells and determining a third cell with the greatest charge excess of the plurality of battery cells; and

discharging the third cell, in order to charge, with a voltage converter, the second cell.

7. The method of claim 1 wherein the discharging occurs during a charging operation of the plurality of battery cells.

8. The method of claim 1 wherein the discharging occurs during the plurality of battery cells providing power to a load.

9. A circuit for controlling an operation of a plurality of battery cells coupled in series, wherein the plurality of battery cells includes at least three cells, the circuit comprising:

sensor circuitry for determining a state of charge of each cell of the plurality of battery cells;

a bus;

a plurality of converter stages each coupled to the bus, wherein

each stage of the plurality of converter stages is associated with a cell of the plurality of battery cells,

each stage of the plurality of converter stages comprises an inductor, a switch, and a capacitor,

each stage of the plurality of converter stages is configurable to serve as a source stage of a voltage converter for discharging the cell associated with the source stage in order to charge, via the bus, another cell of the plurality of battery cells, and

each stage of the plurality of converter stages is configurable to serve as a sink stage for a voltage converter for charging the cell of the plurality of battery cells associated with the sink stage from another cell of the plurality of battery cells via the bus; and

control circuitry for controlling the configuration of the plurality of converter stages.

10. The circuit of claim 9 wherein each stage of the plurality of converter stages is configurable as a source stage for a single ended primary inductor converter (SEPIC) and each stage of the plurality of converter stages is configurable as a sink stage for a single ended primary inductor converter (SEPIC).

11. The circuit of claim 9 wherein the capacitor of each stage of the plurality of converter stages is connected to the bus.

12. The circuit of claim 9 , wherein

when the each converter stage is configured as a source stage of a voltage converter, a first terminal of the inductor is connected to a positive terminal of a cell associated with the each converter stage, and

when the each converter stage is configured as a sink stage of a voltage converter, the first terminal of the inductor is connected to a negative terminal of the cell associated with the each converter stage.

13. The circuit of claim 12 wherein when the each converter stage is configured in a passive configuration, the first terminal of the inductor is not connected to either the positive terminal or the negative terminal of the cell associated with the each converter stage.

14. The circuit of claim 12 , wherein

the switch of each stage of the plurality of converter stages has a first terminal connected to a second terminal of the inductor of each stage, the switch has a second terminal connected to the negative terminal of the cell associated with the each converter stage, and

when the stage that is configured as a source stage of a voltage converter, the control circuitry provides a pulse width modulated signal to control the conductivity of the switch of the stage.

15. The circuit of claim 9 wherein during an equalization operation, the control circuitry configures

a converter stage of the plurality of converter stages associated with a cell of the plurality of battery cells determined to have a greatest charge excess as a source stage of a voltage converter, and

a converter stage of the plurality of converter stages associated with a cell of the plurality of battery cells determined to have a greatest charge deficit as a sink stage of the voltage converter in order to provide charge for charging the cell determined to have the greatest charge deficit.

16. The circuit of claim 9 wherein during an equalization operation, the control circuitry configures no more than one converter stage of the plurality of converter stages as a source stage and no more than one converter stage of the plurality of converter stages as a sink stage.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →