IP Library Granted Patent US 8,847,393
Granted Patent B2
US 8,847,393 · App. 13/036,461 · Granted Sep 30, 2014

Vias between conductive layers to improve reliability

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Quick Facts
Patent No.
US 8,847,393
App. No.
13/036,461
Granted
Sep 30, 2014
Kind
B2
Abstract

Another semiconductor device includes a first layer including a plurality of electrically conductive wires, a second layer, a plurality of non-functional via pads are included in the second layer or between the first layer and the second layer. A dangling via is included within a specified area of the first layer. The dangling vias connect one or more of the wires in the first layer to a respective one of the via pads.

Claims (38)

1. A semiconductor device comprising:

a first layer including a plurality of electrically conductive wires;

a second layer including a plurality of electrically conductive wires;

a non-conductive material between the first layer and the second layer;

a first electrically conductive via through the non-conductive material connecting the first and second layers at an intersection of a first wire on the first layer and a first wire on the second layer at a location where a redundant via is not possible; and

a second electrically conductive via coupled between a second wire on the second layer to a conductive member that is electrically isolated from wires in any other layer of the semiconductor device and sufficiently close to the first electrically conductive via to provide protection to the first electrically conductive via from outgassing problems;

wherein the wires in the first and second layers are smaller than wires that conduct power and ground signals in the semiconductor device.

2. The semiconductor device of claim 1 , wherein the second electrically conductive via is the only via within a predetermined distance from the first via.

3. The semiconductor device of claim 1 , wherein the second electrically conductive via is between the first and second layers.

4. The semiconductor device of claim 1 , wherein the wires in the first layer are perpendicular to the wires in the second layer.

5. The semiconductor device of claim 1 , wherein the conductive member is at least 2 pitches long.

6. The semiconductor device of claim 1 , wherein the second electrically conductive via is the only via between the first and second layers within a predetermined distance from the first electrically conductive via.

7. The semiconductor device of claim 1 , wherein the conductive member is approximately as wide as wire on the second layer.

8. The semiconductor device of claim 1 , wherein the first electrically conductive via and the second electrically conductive via are electrically isolated from one another.

9. A semiconductor device, comprising:

a first layer including a plurality of electrically conductive wires;

a second layer including a plurality of electrically conductive wires;

a non-conductive material between the first layer and the second layer;

a first electrically conductive via through the non-conductive material connecting the first and second layers at an intersection of a first wire on the first layer and a first wire on the second layer and where no redundant via is possible; and

a second electrically conductive via coupled between a second wire on the second layer to a conductive member that is electrically isolated from wires in any other layer of the semiconductor device and is in sufficiently close proximity to the first electrically conductive via to provide protection to the first electrically conductive via from outgassing problems;

wherein pitch between the wires in the first layer is less than a pitch at which a redundant via may be reliably placed between two adjacent wires in the first layer.

10. A semiconductor device comprising:

a first layer including a plurality of electrically conductive wires;

a second layer including a plurality of electrically conductive wires;

a non-conductive material between the first layer and the second layer;

a first electrically conductive via through the non-conductive material connecting the first and second layers at an intersection of a first wire on the first layer and a first wire on the second layer, wherein the first electrically conductive via is in a location where no redundant via is possible; and

a second electrically conductive via, which is a dangling via, coupled between a second wire on the second layer to a conductive member that is electrically isolated from wires in any other layer of the semiconductor device and sufficiently close to the first electrically conductive via to provide protection to the first electrically conductive via from outgassing problems;

wherein the wires in the first layer are smaller than wires that conduct power and ground signals in the semiconductor device.

11. A method of making a semiconductor device comprising:

forming a first conductive layer including a plurality of signal wires;

adding a dielectric layer on top of the first layer;

forming a second conductive layer over the dielectric layer including a plurality of signal wires;

forming an isolated via, wherein the isolated via is coupled between a first wire of the first plurality of signal wires in the first conductive layer and a first wire of the plurality of signal wires in the second conductive layer in a location where a redundant via is not possible; and

forming a dangling via between a second wire in the second layer and the conductive pad, wherein the conductive pad is separated from components in the device other than the dangling via and the dangling via is in sufficiently close proximity to the first electrically conductive via to provide protection to the first electrically conductive via from outgassing problems;

wherein the pluralities of signal wires of the first and second conductive layers are smaller than wires that conduct power and ground signals in the semiconductor device.

12. The method of claim 11 , wherein the dangling via is the only via between the first and second conductive layers within a predetermined distance from the isolated via.

13. The method of claim 11 , further comprising:

forming a plurality of conductive pads and the dangling via to achieve a specified via density between the first and second conductive layers.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2013
From: SHARMA, PUNEET
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030718/0389 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0477 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027621/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2011
From: HOANG, TUAN S.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 025874/0133 →