Patent Application

App. No. 13/245,888

Abstract

Claims (32)

1 . A method of reducing power leakage in an integrated circuit (IC) design defined by IC design data, the IC having a Virtual Multi-Mode Multi-Corner (Virtual MMMC) set up, the method comprising:

providing IC design data to each of a plurality of computing resources, wherein the IC defined by the design data is capable of operating in a number of modes and the IC may be manufactured having a plurality of design corners, wherein each mode and each corner comprises a view;

performing a plurality of first analyses of the design data using the plurality of computing resources, wherein each computer resource analyzes a different view of the IC and generates separate view data;

performing a second analysis based on the plurality of first analyses using a final computing resource, wherein the final computing resource analyzes all of the separate view data and swaps at least one low voltage threshold cell with a high voltage threshold cell; and

updating the IC design data based on the second analysis, the updated design data including the at least one swapped cell.

2 . The method of claim 1 , wherein the final computer resource comprises a randomly selected one of the plurality of computer resources.

3 . The method of claim 1 , wherein each of the plurality of first analyses comprises performing a first timing analysis.

4 . The method of claim 3 , wherein the first timing analysis comprises identifying one or more low threshold voltage cells of the IC having positive slack time.

5 . The method of claim 4 , further comprising swapping at least one of the one or more low threshold voltage cells having positive slack time with a high threshold voltage cell and saving as new view design data.

6 . The method of claim 5 , wherein the swapping is performed in a burst mode, wherein the burst mode comprises substantially simultaneously swapping a plurality of low voltage threshold cells with high voltage threshold cells.

7 . The method of claim 5 , further comprising performing a second timing analysis on the new view design data.

8 . The method of claim 7 , further comprising reverting the swapping of the at least one low voltage threshold cell if the swapping causes the second timing analysis to fail.

9 . The method of claim 8 , wherein in the second analysis, the at least one swapped low threshold voltage cell has positive slack time in each of the plurality of views.

10 . The method of claim 1 , wherein swapping the at least one low threshold cell is performed at a mask layer of the integrated circuit.

11 . A computer implemented system for performing power leakage optimization for an integrated circuit in a Virtual Multi-Mode Multi-Corner (Virtual MMMC) set up, the system comprising:

a generating module configured for generating design data for the integrated circuit;

a plurality of primary modules configured for performing a plurality of first analyses, wherein each of the plurality of first analyses is performed using a separate and independent primary module of the plurality of primary modules; and

a secondary module configured for performing a second analysis based on the plurality of first analyses.

12 . The system of claim 10 , wherein the view module generates a view of the integrated circuit based on the design data, wherein the view comprises one of a mode, a corner, and a combination of a mode and a corner of the integrated circuit.

13 . The system of claim 12 , wherein the analysis module performs a timing analysis and provides timing data to the swapping module.

14 . The system of claim 12 , wherein the swapping module swaps low threshold voltage cells and higher threshold voltage cells of the integrated circuit based on the timing data.

15 . The system of claim 11 , wherein the secondary module comprises an input module, an operation module, and a recovery module.

16 . The system of claim 15 , wherein the input module transfers the timing data and swap information received from the analysis module and swapping module respectively to the operation module.

17 . The system of claim 15 , wherein the operation module provides recovery information to the recovery module based on intersection and union operations performed on the timing data and swap information.

18 . The system of claim 15 , wherein the recovery information comprises a list of cells having positive slack time in all of the views.

19 . The system of claim 18 , wherein the recovery module recovers all of the cells in the list.

20 . A computer program product for use with a computer, the computer program product comprising a non-transitory computer usable medium having a computer readable program code embodied therein for performing power leakage optimization for an integrated circuit in a Virtual Multi-Mode Multi-Corner (Virtual MMMC) set up, the computer readable program code having instructions for:

generating design data for the integrated circuit having a plurality of modes and a plurality of corners, wherein generating the design data comprises generating a plurality of views of the integrated circuit;

providing the design data to each of a plurality of computing resources;

performing a plurality of first analyses of the design data using the plurality of computing resources, wherein each of the plurality of first analyses is performed by a separate and independent computing resource randomly selected from the plurality of computing resources;

performing a second analysis based on the plurality of first analyses using a final computing resource, wherein the final computing resource is randomly selected from the plurality of computing resources; and

recovering at least one low threshold voltage cell of a plurality of cells of the integrated circuit based on the second analysis.

Assignments (27)