Method to form a via
View Patent ↗A method for forming a via, comprising (a) providing a structure comprising a mask ( 210 ) disposed on a semiconductor substrate ( 203 ), wherein the structure has an opening ( 215 ) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer ( 219 ) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal ( 221 ) over the first portion of the second conductive layer.
1. A semiconductor fabrication method, comprising:
creating a mask over a substrate, the mask comprising a mask metal layer disposed between a first dielectric layer and a second dielectric layer wherein the mask metal layer prevents contact between the first dielectric layer and the second dielectric layer, the mask having an opening defined therein which exposes a portion of the substrate and a portion of the mask metal layer;
etching the exposed portion of the substrate to create a via therein;
depositing an electrically conductive barrier layer over surfaces of the via;
depositing a metal seed layer over the barrier layer and in electrical contact with the mask metal layer;
removing the metal seed layer exterior to the via; and
performing an electroplating process to fill the via.
2. The method of claim 1 , wherein the electroplating process uses the metal seed layer as a conductive element.
3. The method of claim 1 , wherein the substrate is a wafer, and further comprising removing a portion of at least one of the first and second dielectric layers from the edge of the wafer prior to performing the electroplating process.
4. The method of claim 1 , wherein the metal seed layer has a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening.
5. The method of claim 4 , wherein the barrier layer has a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening, wherein the barrier layer is in electrical contact with the mask metal layer, and wherein the step of removing the second portion of the metal seed layer also removes the second portion of the barrier layer.
6. The method of claim 5 , wherein the seed layer is deposited over the barrier layer.
7. The method of claim 6 , wherein the barrier layer is a metal barrier layer.
8. The method of claim 1 , wherein the metal seed layer comprises copper, and wherein filling the via by way of an electroplating process comprises filling the via with copper.
9. The method of claim 5 , wherein the second portion of the metal seed layer is removed from the portion of the mask adjacent to the opening through chemical mechanical polishing (CMP).
10. The method of claim 1 , wherein the first and second dielectric layers comprise a material selected from the group consisting of tetraethylorthosilicate (TEOS), diamond-like carbon, silicon oxide, silicon nitride and aluminum oxide.
11. The method of claim 1 , wherein the first and second dielectric layers comprise tetraethylorthosilicate (TEOS).
12. The method of claim 1 wherein, prior to deposition of the metal seed layer, a third dielectric layer is formed over the surfaces of the opening.
13. The method of claim 12 , wherein the third dielectric layer is in contact with the semiconductor substrate.
14. The method of claim 12 , wherein the third dielectric layer is formed by a plasma nitridation step.
15. The method of claim 1 , wherein the substrate is a wafer.
16. The method of claim 1 , wherein the electroplating process involves electrochemical deposition, and wherein at least one of the first and second dielectric layers is removed from the edge of the wafer by etching prior to the electrochemical deposition.
17. The method of claim 1 , wherein the opening is a through semiconductor via (TSV).
18. The method of claim 1 , wherein the mask metal layer comprises a metal selected from the group consisting of titanium, titanium nitride, chromium, nickel and copper.
19. The method of claim 3 , wherein removing a portion of at least one of the first and second dielectric layers from the edge of the wafer comprises etching at least one of the first and second dielectric layers in a reactive ion etching (RIE) chamber with a material selected from the group consisting of CF 4 , CHF 3 , C2F 6 , C3F 8 , C4F 8 , SF 6 , NF 3 , C 4 F 6 , C 5 F 8 , and HF.
20. The method of claim 1 , wherein the exposed portion of the substrate is either (a) etched with a dry etch based on a material selected from the group consisting of CF 4 , SF 6 , NF 3 , CHF 3 , C 4 F 8 , CHCl 3 , O 2 , Cl 2 and Br 2 , or (b) etched with a wet etch based on a material selected from the group consisting of HF, NaOH, KOH, H 2 O 2 , ethylene diamine, and ethanolamine.