Partially depleted dielectric resurf LDMOS
View Patent ↗An partially depleted Dieler LDMOSFET transistor ( 100 ) is provided which includes a substrate ( 150 ), a drift region ( 110 ) surrounding a drain region ( 128 ), a first well region ( 107 ) surrounding source region ( 127 ), a well buffer region ( 106 ) separating the drift region and first well region to at least partly define a first channel region, a gate electrode ( 118 ) formed over the first channel region having a source-side gate edge aligned with the first well region ( 107 ), an LDD extension region ( 120 ) extending from the source region to the channel region, and a dielectric RESURF drain extension structure ( 161 ) formed at the drain of the gate electrode ( 118 ) using the plurality of STI stripes ( 114 ).
1. A semiconductor device, comprising:
a first heavily doped semiconductor region of a first conductivity type located in a substrate;
a first source region of a second conductivity type different from the first conductivity type that is located in a predetermined upper region of the first heavily doped semiconductor region;
a second heavily doped semiconductor drift region of the second conductivity type formed in the substrate to be spaced apart from the first heavily doped semiconductor region;
a first drain region of the second conductivity type formed in a predetermined upper region of the second heavily doped semiconductor drift region, the first drain region being spaced a predetermined distance from the first heavily doped semiconductor region;
a third lightly doped semiconductor region of the first conductivity type formed in the substrate to surround the first heavily doped semiconductor region, thereby separating the first heavily doped semiconductor region from the second heavily doped semiconductor drift region to form at least part of a channel region;
a gate electrode and a gate insulating layer formed over the channel region; and
a plurality of insulator strips formed at a surface of the substrate to define one or more drain extension structures in at least the second heavily doped semiconductor drift region between the first drain region and gate electrode.
2. The semiconductor device of claim 1 , where the first conductivity type is p-type, and the second conductivity type is n-type.
3. The semiconductor device of claim 1 , wherein the first heavily doped semiconductor region comprises a p-type well located at the surface of the substrate.
4. The semiconductor device of claim 1 , wherein the second heavily doped semiconductor drift region comprises an n-type well located at the surface of the substrate.
5. The semiconductor device of claim 1 , where the third lightly doped semiconductor region comprises a p-type epitaxial layer in which the first heavily doped semiconductor region and second heavily doped semiconductor drift region are formed.
6. The semiconductor device of claim 1 , where the plurality of insulator strips comprises a plurality of shallow trench isolation strips formed to a depth that is shallower than the second heavily doped semiconductor drift region.
7. The device of claim 6 , where the one or more drain extension structures comprise one or more narrow p-n diode structures, each having a diode junction between the third lightly doped semiconductor region and the second heavily doped semiconductor drift region.
8. The semiconductor device of claim 1 , further comprising a fourth lightly doped high voltage semiconductor region of the second conductivity type located in the third lightly doped semiconductor region and adjacent to the second heavily doped semiconductor drift region and to a depth that is shallower than the second heavily doped semiconductor drift region, thereby separating a portion of the third lightly doped semiconductor region at a surface of the substrate from the second heavily doped semiconductor drift region to form at least part of the channel region.
9. The semiconductor device of claim 8 , where the fourth lightly doped high voltage semiconductor region comprises a lightly doped n-type high voltage n-well buffer.
10. The device of claim 9 , where the plurality of insulator strips comprises a plurality of shallow trench isolation strips formed to define one or more drain extension structures in the second heavily doped semiconductor drift region and the fourth lightly doped high voltage semiconductor region.
11. A method of fabricating a semiconductor device, comprising in any order:
forming a first doped well of a first conductivity type within a first lightly doped region, where the first doped well is disposed to surround a designated source region area and has a first lateral edge extending to a surface of a semiconductor substrate;
forming in the designated source region area of the first doped well a first source region of a second, opposite, conductivity type;
forming in the semiconductor substrate a second doped well of the second conductivity type having a second lateral edge extending to a surface of the semiconductor substrate and spaced apart from the first lateral edge, where second doped well is disposed to surround a designated drain region area, thereby forming a PN junction with first lightly doped substrate region at the surface of the semiconductor substrate;
forming in the designated drain region area of the second doped well a first drain region of the second conductivity type;
forming a plurality of insulator strips at the surface of the semiconductor substrate to define one or more narrow diode structures across the PN junction that extend between the first drain region and a designated gate electrode region; and
forming a gate electrode overlying the surface of the semiconductor substrate at the designated gate electrode region.
12. The method of claim 11 , where the first conductivity type is p-type, and the second conductivity type is n-type.
13. The method of claim 11 , further comprising implanting a lightly doped source extension region which extends under the first side edge of the gate electrode from the first source region and first doped well and into the first lightly doped substrate region.
14. The method of claim 11 , where forming the gate electrode comprises forming a gate electrode overlying the surface of the semiconductor substrate at the designated gate electrode region, wherein a first side edge of the gate electrode is substantially aligned with the first lateral edge of the first doped well, and a second opposite side edge of the gate electrode is substantially aligned with the second lateral edge of the second doped well.
15. The method of claim 11 , where forming the plurality of insulator strips comprises forming a plurality of shallow trench isolation strips to a depth that is shallower than the second doped well.
16. The method of claim 11 , where forming the second doped well comprises forming a heavily doped epitaxial n-type drift region located at the surface of the semiconductor substrate to surround the first drain region.
17. A method for forming an LDMOS device, comprising:
providing a semiconductor substrate having a first lightly doped p-type region extending to a surface of the semiconductor region in at least a first channel region;
forming first and second wells in the semiconductor substrate spaced apart by at least the first lightly doped p-type region, where the first well is a p-type well for containing a source region and having a first lateral edge extending to a surface of the semiconductor substrate, and where the second well is an n-well for containing a drain region and having a second lateral edge extending to the surface of the semiconductor substrate;
forming a plurality of insulator strips in an upper surface region of at least the second well to define one or more drain extension structures that extend from a designated drain region area to a designated gate electrode region area;
forming a gate electrode insulated from the surface overlying the first lightly doped p-type region;
using the gate electrode as at least a partial mask, implanting impurities into the semiconductor substrate to form a lightly doped n-type source extension region which overlaps with the first side edge of the gate electrode; and
implanting n-type source and drain regions into the first and second wells, respectively, so that the source region is located within the first well to be spaced apart from the first lateral edge, and the drain region is located in the second well to be spaced apart from the second lateral edge.
18. The method of claim 17 , where forming the forming a plurality of insulator strips comprises forming a plurality of shallow trench isolation regions to a depth that is shallower than the second well.
19. The method of claim 17 , further comprising forming a lightly doped n-well in the semiconductor substrate adjacent to the second well and spaced apart from the first well by at least the first lightly doped p-type region so that the lightly doped n-well and first lightly doped p-type region separate the first and second wells to form at least part of the first channel region.
20. The method of claim 19 , where forming the lightly doped n-well comprises implanting a lightly doped n-type high voltage n-well buffer region.