Semiconductor device with a controlled cavity and method of formation
View Patent ↗A semiconductor device includes a first cap wafer having a first opening extending through the first cap wafer, and a second cap wafer bonded to the first cap wafer, wherein the second cap wafer has a second opening extending through the second cap wafer, and wherein the first opening is misaligned with respect to the second opening. The second cap wafer is bonded to a device wafer, wherein a cavity is formed between the device wafer and the second cap wafer, and wherein the device wafer comprises at least one semiconductor device in the cavity. A vacuum sealing layer is formed over the first cap wafer, wherein the sealing layer vacuum seals the first opening.
1. A semiconductor device comprising:
a first cap wafer having a first opening extending through the first cap wafer, and a second cap wafer bonded to the first cap wafer, wherein the second cap wafer has a second opening extending through the second cap wafer, wherein the first opening is misaligned with respect to the second opening;
a cavity between a device wafer and the second cap wafer, and wherein the device wafer comprises at least one semiconductor device exposed to the cavity; and
a sealing layer over the first cap wafer, wherein the sealing layer vacuum seals the first opening.
2. The semiconductor device of claim 1 , wherein the first cap wafer has a first major surface and a second major surface opposite the first major surface, and the second cap wafer has a first major surface and a second major surface opposite the first major surface, wherein the second major surface of the first cap wafer is between the first major surface of the first cap wafer and the first major surface of the second cap wafer, and the first major surface of the second cap wafer is between the second major surface of the first cap wafer and the second major surface of the second cap wafer, and wherein second major surface of the first cap wafer is bonded to the first major surface of the second cap wafer.
3. The semiconductor device of claim 2 , wherein the second major surface of the first cap wafer is bonded to the first major surface of the second cap wafer with a bonding layer and wherein the second major surface of the first cap wafer is spaced apart from the first major surface of the second cap wafer such that a vent path is present from the first opening to the second opening, between the second major surface of the first cap wafer and the first major surface of the second cap wafer.
4. The semiconductor device of claim 2 , wherein at least one of the second major surface of the first cap wafer or the first major surface of the second cap wafer includes a trench such that a vent path is present from the first opening to the second opening via the trench.
5. The semiconductor device of claim 4 , wherein the first cap wafer and the second cap wafer are laminated together.
6. The semiconductor device of claim 1 , wherein the first cap wafer comprises a first plurality of openings, each extending through the first cap wafer, wherein the first plurality of openings comprises the first opening, and the second cap wafer comprises a second plurality of openings, each extending through the second cap wafer, wherein the second plurality of openings comprises the second opening.
7. The semiconductor device of claim 6 , wherein each opening of the first plurality of openings is misaligned with respect to each opening of the second plurality of openings.
8. The semiconductor device of claim 7 , wherein the sealing layer seals each opening of the first plurality of openings.
9. The semiconductor device of claim 1 , wherein the semiconductor device comprises a micro-electro-mechanical (MEM) device.
10. The semiconductor device of claim 1 , wherein the sealing layer is formed within the first opening.
11. A semiconductor device comprising:
a first cap wafer having one or more openings extending through the first cap wafer, and a second cap wafer bonded to the first cap wafer, wherein the second cap wafer has one or more openings extending through the second cap wafer, wherein each of the one or more openings in the first cap wafer is misaligned with respect to each of the one or more openings in the second cap wafer;
the second cap wafer is bonded to a device wafer, wherein a cavity is formed between the device wafer and the second cap wafer, wherein a vent path is present from the cavity through the one or more openings in the second cap wafer and through the one or more openings in the first cap wafer, and wherein the device wafer comprises at least one semiconductor device within the cavity; and
a sealing layer over the first cap wafer, wherein the sealing layer seals each opening of the one or more openings in the first cap wafer, and wherein the first cap wafer is located between the sealing layer and the second cap wafer.
12. The semiconductor device of claim 11 , wherein the first cap wafer is spaced apart from the second cap wafer, and wherein the vent path is present from the cavity through the one or more openings extending through the first cap wafer, between the first cap wafer and the second cap wafer, and through the one or more openings extending through the second cap wafer.
13. The semiconductor device of claim 11 , wherein at least one of the first cap wafer or the second cap wafer includes a trench, and wherein the vent path is present from the cavity through the one or more opening extending through the first cap wafer, through the trench, and through the one or more openings extending through the second cap wafer.
14. The semiconductor device of claim 13 , wherein the first cap wafer and the second cap wafer are laminated together.
15. The semiconductor device of claim 11 , wherein the semiconductor device comprises a MEM device.
16. The semiconductor device of claim 11 , wherein the sealing layer is formed within the one or more openings in the first cap wafer.
17. The semiconductor device of claim 11 , wherein the device wafer, the first cap wafer, and the second cap wafer are singulated from one another.
18. A semiconductor device, comprising:
a first cap layer having one or more openings extending through the first cap layer;
a second cap layer bonded to the first cap layer, the second cap layer having one or more openings extending through the second cap layer, wherein each of the one or more openings in the first cap layer are misaligned with respect to each of the one or more openings in the second cap layer;
a sealing layer over the first cap layer, wherein the first cap layer is located between the sealing layer and the second cap layer, and wherein the sealing layer seals each of the one or more openings in the first cap layer;
a device layer bonded to the second cap layer and comprising a MEM device; and
a vacuum cavity between the device layer and the second cap layer, wherein the MEM device is in the vacuum cavity.
19. The semiconductor device of claim 18 , further comprising:
a vent path from a first opening of the one or more openings in the second cap layer to a second opening of the one or more openings in the first cap layer, the vent path located between the second cap layer and the first cap layer.
20. The semiconductor device of claim 18 , further comprising:
a vent path from a first opening of the one or more openings in the second cap layer to a second opening of the one or more openings in the first cap layer, the vent path located in at least one of the first cap layer or the second cap layer.