IP Library Granted Patent US 8,081,026
Granted Patent B1
US 8,081,026 · App. 12/787,457 · Granted Dec 20, 2011

Method for supplying an output supply voltage to a power gated circuit and an integrated circuit

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Quick Facts
Patent No.
US 8,081,026
App. No.
12/787,457
Granted
Dec 20, 2011
Kind
B1
Abstract

An integrated circuit, that includes: (i) a power gating switch, the power gating switch includes (a) an input port for receiving an input supply voltage; (b) an output port for outputting an output supply voltage; and (c) a control port for receiving a control signal that determines a difference between a value of the input supply voltage and a value of the output supply voltage; (ii) a power gated circuit, coupled to the output port of the switch, for receiving the output supply voltage; (iii) a mode indicator generator for generating a mode indicator that indicates of a desired mode of the power gated circuit; (iv) a leakage indicator generator for generating a leakage indicator that indicates of a leakage level of the power gated circuit; and (iv) a control circuit, for receiving the mode indicator and the leakage indicator, and for selecting the value of the control signal based on the mode indicator and on the leakage indicator.

Claims (46)

1. An integrated circuit, comprising:

a power gating switch, the switch comprises:

an input port for receiving an input supply voltage;

an output port for providing an output supply voltage to a power gated circuit; and

a control port for receiving a control signal that determines a difference between the input supply voltage and the output supply voltage;

wherein the integrated circuit further comprising the power gated circuit, being gated relative to the input supply voltage by the switch, the power gated circuit being coupled to the output port of the switch for receiving the output supply voltage;

a mode indicator generator for generating a mode indicator that indicates a desired mode of the power gated circuit; a leakage indicator generator for generating a leakage indicator that indicates a leakage level of the power gated circuit; and

a control circuit, connected to the mode indicator generator and the leakage indicator generator, for receiving the mode indicator and the leakage indicator, the control circuit being arranged to select the value of the control signal based on the mode indicator and on the leakage indicator.

2. The integrated circuit according to claim 1 , wherein the control circuit is arranged to:

select a performance value of the control signal when (i) the leakage indicator indicates that a leakage of the power gated circuit is below a low leakage threshold and (ii) the mode indicator indicates that the power gated circuit is requested to operate at a performance oriented mode;

select a leakage reduction value of the control signal when (i) the leakage indicator indicates that the leakage of the power gated circuit is above the low leakage threshold and (ii) the mode indicator indicates that the power gated circuit is requested to operate at the performance oriented mode; and

select a shut down value of the control signal when the mode indicator indicates that the power gated circuit should be shut down.

3. The integrated circuit according to claim 2 , wherein the control circuit is arranged to select the leakage reduction value out of a group of leakage reduction values based on a temperature of the integrated circuit.

4. The integrated circuit according to claim 2 , wherein the control circuit is arranged to select the leakage reduction value out of a group of leakage reduction values based on a temperature of the integrated circuit and on the leakage indicator of the integrated circuit.

5. The integrated circuit according to claim 2 , wherein the control circuit is arranged to select a retention value of the control signal when the mode indicator indicates that the power gated circuit is requested to enter a retention mode.

6. The integrated circuit according to claim 5 , wherein the control circuit is arranged to select a retention value out of a group of retention values based on a temperature of the integrated circuit.

7. The integrated circuit according to claim 5 , wherein the control circuit is arranged to select the retention value out of a group of retention values based on a temperature of the integrated circuit and on the leakage indicator.

8. The integrated circuit according to claim 2 , wherein the control circuit is arranged to:

select the performance value of the control signal when the leakage indicator indicates that the integrated circuit is slow in comparison to most integrated circuits of a batch of integrated circuits that comprises the integrated circuit, and (ii) the mode indicator indicates that the power gated circuit is requested to operate at a performance oriented mode.

9. The integrated circuit according to claim 1 , further comprising:

a temperature module connected to the control circuit, the temperature module arranged to provide a temperature indication that indicates a temperature of the integrated circuit to the control circuit.

10. The integrated circuit according to claim 9 , wherein the temperature module is arranged to:

estimate a temperature of the power gated circuit based on electrical measurements of the power gated circuit that reflect the temperature of the power gated circuit.

11. The integrated circuit according to claim 9 , wherein the temperature module is arranged to:

estimate a temperature of the power gated circuit based on speed measurements of the power gated circuit that reflect the temperature of the power gated circuit.

12. The integrated circuit according to claim 11 , wherein the control circuit is arranged to:

select the leakage reduction value of the control signal when (i) the leakage indicator indicates that the integrated circuit is fast in comparison to most integrated circuits of a batch of integrated circuits that comprises the integrated circuit, and (ii) the mode indicator indicates that the power gated circuit is requested to operate at the performance oriented mode.

13. A method for supplying an output supply voltage to a power gated circuit, the method comprising:

providing to an input port of a power gating switch an input supply voltage;

receiving, by a control circuit, a mode indicator that indicates of a desired mode of the power gated circuit;

receiving, by the control circuit, a leakage indicator that indicates of a leakage level of the power gated circuit;

selecting, by the control circuit, a value of a control signal based on the mode indicator and on the leakage indicator;

supplying the control signal to a control port of the power gating switch;

providing, from an output port of the power gating switch, the output supply voltage to the power gated circuit; wherein a relationship between a value of the input supply voltage and a value of the output supply voltage is responsive to the value of the control signal.

14. The method according to claim 13 , comprising:

selecting a performance value of the control signal when (i) the leakage indicator indicates that a leakage of the power gated circuit is below a low leakage threshold and (ii) the mode indicator indicates that the power gated circuit is requested to operate at a performance oriented mode;

selecting a leakage reduction value of the control signal when (i) the leakage indicator indicates that the leakage of the power gated circuit is above the low leakage threshold and (ii) the mode indicator indicates that the power gated circuit is requested to operate at the performance oriented mode; and

selecting a shut down value of the control signal when the mode indicator indicates that the power gated circuit should be shut down.

15. The method according to claim 14 , comprising:

selecting the performance value of the control signal when the leakage indicator indicates that the integrated circuit is slow in comparison to most integrated circuits of a batch of integrated circuits that comprises the integrated circuit, and (ii) the mode indicator indicates that the power gated circuit is requested to operate at the performance oriented mode; and

selecting the leakage reduction value of the control signal when (i) the leakage indicator indicates that the integrated circuit is fast in comparison to most integrated circuits of a batch of integrated circuits that comprises the integrated circuit, and (ii) the mode indicator indicates that the power gated circuit is requested to operate at the performance oriented mode.

16. The method according to claim 14 , comprising selecting the leakage reduction value out of a group of leakage reduction values based on a temperature of the integrated circuit.

17. The method according to claim 14 , comprising selecting the leakage reduction value out of a group of leakage reduction values based on a temperature of the integrated circuit and on the leakage indicator.

18. The method according to claim 14 , comprising selecting a retention value of the control signal when the mode indicator indicates that the power gated circuit is requested to enter a retention mode.

19. The method according to claim 18 , comprising selecting the retention value out of a group of retention values based on a temperature of the integrated circuit.

20. The method according to claim 18 , wherein comprising selecting the retention value out of a group of retention values based on a temperature of the integrated circuit and on the leakage indicator.

Assignments (33)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP USA, INC. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 042610/0451 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2017
From: NXP USA, INC.
To: VLSI TECHNOLOGY LLC
Reel/Frame 042374/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0477 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2010
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To: FREESCALE SEMICONDUCTOR INC.
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