IP Library › Assignment 042610/0451
Patent Assignment
Reel/Frame 042610/0451

RELEASE OF SECURITY INTEREST

Recorded: 2017-05-29 Received: 2017-05-29 Pages: 12
Assignor
Assignee
NXP USA, INC. F/K/A FREESCALE SEMICONDUCTOR, INC.
6501 WILLIAM CANNON DRIVE WEST, AUSTIN, TX, 78735, UNITED STATES
Covered Applications (45)
Method of Forming Different Voltage Devices with High-K Metal Gate
App. No. 14/843,364
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APPARATUS AND METHOD FOR PREVENTING MULTIPLE RESETS
App. No. 14/269,194
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Method of Forming Different Voltage Devices with High-K Metal Gate
App. No. 14/021,485
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SYSTEM AND METHOD FOR LOW-LATENCY ADDRESSING IN FLASH MEMORY
App. No. 13/925,807
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DYNAMIC READ SCHEME FOR HIGH RELIABILITY HIGH PERFORMANCE FLASH MEMORY
App. No. 13/679,481
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INTEGRATED CIRCUIT DEVICE, CALIBRATION MODULE, AND METHOD THEREFOR
App. No. 13/634,726
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SENSING DEVICE AND RELATED OPERATING METHODS
App. No. 13/523,675
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STACKED DIE SEMICONDUCTOR PACKAGE
App. No. 13/490,451
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MRAM DEVICE AND METHOD OF ASSEMBLING SAME
App. No. 13/334,006
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METHOD FOR SUPPLYING AN OUTPUT SUPPLY VOLTAGE TO A POWER GATED CIRCUIT AND AN INTEGRATED CIRCUIT
App. No. 12/787,457
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PHASE-LOCKED LOOP HAVING A FEEDBACK CLOCK DETECTOR CIRCUIT AND METHOD THEREFOR
App. No. 12/695,461
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SYSTEM AND METHOD FOR COMMUNICATING BETWEEN MULTIPLE VOLTAGE TIERS
App. No. 12/621,026
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SYSTEM HAVING MULTIPLE VOLTAGE TIERS AND METHOD THEREFOR
App. No. 12/621,005
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Multi-Core System on Chip
App. No. 12/618,311
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REGULATOR HAVING INTERLEAVED LATCHES
App. No. 12/555,227
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VOLTAGE BOOSTING SYSTEM WITH SLEW RATE CONTROL AND METHOD THEREOF
App. No. 12/537,436
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MEMORY USING MULTIPLE SUPPLY VOLTAGES
App. No. 12/487,791
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SEMICONDUCTOR SUBSTRATE AND METHOD OF CONNECTING SEMICONDUCTOR DIE TO SUBSTRATE
App. No. 12/471,409
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SOFT ERROR AND TRANSIENT ERROR DETECTION DEVICE AND METHODS THEREFOR
App. No. 12/415,338
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MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF
App. No. 12/209,477
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DEVICE AND METHOD FOR CONFIGURING INPUT/OUTPUT PADS
App. No. 12/092,463
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METHOD AND DEVICE FOR HIGH SPEED TESTING OF AN INTEGRATED CIRCUIT
App. No. 11/914,700
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METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES
App. No. 11/914,079
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METHOD FOR NOISE REDUCTION IN A PHASE LOCKED LOOP AND A DEVICE HAVING NOISE REDUCTION CAPABILITIES
App. No. 11/910,062
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METHOD AND APPARATUS FOR AFFECTING A PORTION OF AN INTEGRATED CIRCUIT
App. No. 11/624,454
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BYTE WRITEABLE MEMORY WITH BIT-COLUMN VOLTAGE SELECTION AND COLUMN REDUNDANCY
App. No. 11/612,626
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LOW VOLTAGE MEMORY DEVICE AND METHOD THEREOF
App. No. 11/435,942
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MEMORY WITH LEVEL SHIFTING WORD LINE DRIVER AND METHOD THEREOF
App. No. 11/433,998
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ARRANGEMENT, PHASE LOCKED LOOP AND METHOD FOR NOISE SHAPING IN A PHASE-LOCKED LOOP
App. No. 10/537,634
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BIT LINE PRECHARGE IN EMBEDDED MEMORY
App. No. 11/362,694
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PROCESS FOR FORMING AN ELECTRONIC DEVICE INCLUDING A FIN-TYPE STRUCTURE
App. No. 11/328,668
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VOLTAGE CONTROLLED OSCILLATOR HAVING DIGITALLY CONTROLLED PHASE ADJUSTMENT AND METHOD THEREFOR
App. No. 11/251,467
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CASCADABLE LEVEL SHIFTER CELL
App. No. 11/170,398
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INTEGRATED CIRCUIT HAVING STRUCTURAL SUPPORT FOR A FLIP-CHIP INTERCONNECT PAD AND METHOD THEREFOR
App. No. 11/033,009
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MEMORY BIT LINE SEGMENT ISOLATION
App. No. 10/912,824
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TEMPERATURE COMPENSATED ON-CHIP BIAS CIRCUIT FOR LINEAR RF HBT POWER AMPLIFIERS
App. No. 10/857,040
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Integrated circuit with a transistor over an interconnect layer
App. No. 10/423,589
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FLIP-CHIP STRUCTURE AND METHOD FOR HIGH QUALITY INDUCTORS AND TRANSFORMERS
App. No. 10/329,081
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METHOD FOR FORMING A COPPER INTERCONNECT USING A MULTI-PLATEN CHEMICAL MECHANICAL POLISHING (CMP) PROCESS
App. No. 10/175,637
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METHOD AND APPARATUS FOR AFFECTING A PORTION OF AN INTEGRATED CIRCUIT
App. No. 10/157,094
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DUAL STEERED FREQUENCY SYNTHESIZER
App. No. 09/968,178
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MULTIPHASE VOLTAGE CONTROLLED OSCILLATOR
App. No. 09/968,171
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METHOD OF FORMING A BOND PAD AND STRUCTURE THEREOF
App. No. 09/952,527
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METHOD FOR ADDING FEATURES TO A DESIGN LAYOUT AND PROCESS FOR DESIGNING A MASK
App. No. 09/906,874
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METHOD FOR FORMING A COPPER INTERCONNECT USING A MULTI-PLATEN CHEMICAL MECHANICAL POLISHING (CMP) PROCESS
App. No. 09/835,276
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