Memory with level shifting word line driver and method thereof
View Patent ↗A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.
1. In a memory comprising address decode circuitry operable at a first voltage and comprising word line driver circuitry and a bit cell array operable at a second voltage greater than the first voltage, a method comprising:
in an active mode:
powering the address decode circuitry at the first voltage; and
powering the word line driver circuitry and the bit cell array at the second voltage; and
in a low power mode:
powering the address decode circuitry at a third voltage less than the first voltage, wherein the address decode circuitry is substantially inoperable at the third voltage; and
powering the bit cell array at a fourth voltage not greater than the second voltage, wherein the bit cell array is operable to retain stored data at the fourth voltage.
2. The method of claim 1 , wherein the third voltage is substantially zero.
3. The method of claim 1 , wherein the fourth voltage is substantially equal to the second voltage.
4. The method of claim 1 , wherein:
powering the word line driver circuitry at the second voltage comprises powering word line driver circuitry comprising a plurality of outputs at the second voltage, each output coupled to a corresponding word line of the bit cell array; and
the method further comprises:
voltage level shifting an output of the plurality of outputs from the first voltage to the second voltage.
5. The method of claim 1 , wherein:
the address decode circuitry comprises a first plurality of transistors having a first gate oxide thickness; and
the word line driver circuitry and the bit cell array comprise a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness.
6. The method of claim 5 , wherein powering the word line driver circuitry and the bit cell array at the second voltage comprises providing the second voltage to a voltage level shifter of the word line driver circuitry, the voltage level shifter comprising:
a first transistor having a gate electrode coupled to receive a corresponding bit value of the first predecode value, a first current electrode coupled to receive a corresponding bit value of a second predecode value, and a second current electrode coupled to a first node of the voltage level shifter;
a second transistor having a gate electrode to receive the second voltage, a first current electrode coupled to a ground voltage reference, and a second current electrode coupled to the first node of the voltage level shifter;
a third transistor having a gate electrode coupled to the first node of the voltage level shifter, a first current electrode to receive the second voltage, and a second current electrode coupled to a second node of the voltage level shifter;
a fourth transistor having a gate electrode coupled to the first node, a first current electrode coupled to the second node of the voltage level shifter, and a second current electrode coupled to the ground voltage reference;
wherein the second node of the voltage level shifter is coupled to a corresponding word line of the bit cell array; and
wherein the first transistor, second transistor, third transistor and fourth transistor have the second gate oxide thickness.
7. The method of claim 1 , wherein the fourth voltage is substantially equal to the fifth voltage.
8. A memory operable in an active mode and in a low power mode, the memory comprising:
a first voltage domain and a second voltage domain;
address decode circuitry operated in the first voltage domain and comprising a first plurality of transistors having a first gate oxide thickness;
word line driver circuitry and a bit cell array operated in the second voltage domain and comprising a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness;
a first power supply for the first voltage domain;
a second power supply for the second voltage domain;
a mode controller configured to:
in the active mode:
configure the first power supply to provide a first voltage to the first voltage domain, wherein the address decode circuitry is operable at the first voltage; and
configure the second power supply to provide a second voltage to the second voltage domain, wherein the second voltage is greater than the first voltage and the word line driver circuitry, and the bit cell array are operable at the second voltage; and
in the low power mode:
configure the first power supply to provide a third voltage to the first voltage domain, wherein the third voltage is less than the first voltage and the address decode circuitry is substantially inoperable at the third voltage; and
configure the second power supply to provide a fourth voltage to the second voltage domain, wherein the fourth voltage is not greater than the second voltage and the bit cell array is operable to retain stored data at the fourth voltage.
9. The memory of claim 8 , wherein the third voltage is substantially zero.
10. The memory of claim 8 , wherein the fourth voltage is substantially equal to the second voltage.
11. The memory of claim 8 , wherein the word line driver circuitry comprises:
a voltage level shifter comprising:
a first transistor having a gate electrode coupled to receive a corresponding bit value of a first predecode value, a first current electrode coupled to receive a corresponding bit value of a second predecode value, and a second current electrode coupled to a first node of the voltage level shifter;
a second transistor having a gate electrode coupled to a ground voltage reference, a first current electrode coupled to an output of the second power supply, and a second current electrode coupled to the first node of the voltage level shifter;
a third transistor having a gate electrode coupled to the first node of the voltage level shifter, a first current electrode coupled to the output of the second power supply, and a second current electrode coupled to a second node of the voltage level shifter;
a fourth transistor having a gate electrode coupled to the first node, a first current electrode coupled to the second node of the voltage level shifter, and a second current electrode coupled to the ground voltage reference;
wherein the second node of the voltage level shifter is coupled to a corresponding word line of the bit cell array; and
wherein the first transistor, second transistor, third transistor and fourth transistor have the second gate oxide thickness.
12. The memory of claim 8 , wherein the first gate oxide thickness is less than 14 angstroms and wherein the second gate oxide thickness is less than 19 angstroms.
13. The method of claim 5 , wherein the first gate oxide thickness is less than 14 angstroms and wherein the second gate oxide thickness is less than 19 angstroms.
14. A memory comprising:
address decode circuitry operable at a first voltage and configured to provide a first predecode value and a second predecode value for a corresponding address value, the address decode circuitry comprising a first plurality of transistors having a first gate oxide thickness;
word line driver circuitry and a bit cell array operable at a second voltage greater than the first voltage, the word line driver circuitry and the bit cell array comprising a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness;
the word line driver circuitry comprising a voltage level shifter, the voltage level shifter comprising:
a first transistor having a gate electrode coupled to receive a corresponding bit value of the first predecode value, a first current electrode coupled to receive a corresponding bit value of the second predecode value, and a second current electrode coupled to a first node of the voltage level shifter;
a second transistor having a gate electrode coupled to a ground voltage reference, a first current electrode to receive the second voltage, and a second current electrode coupled to the first node of the voltage level shifter;
a third transistor having a gate electrode coupled to the first node of the voltage level shifter, a first current electrode to receive the second voltage, and a second current electrode coupled to a second node of the voltage level shifter;
a fourth transistor having a gate electrode coupled to the first node, a first current electrode coupled to the second node of the voltage level shifter, and a second current electrode coupled to the ground voltage reference;
wherein the second node of the voltage level shifter is coupled to a corresponding word line of the bit cell array; and
wherein the first transistor, second transistor, third transistor and fourth transistor have the second gate oxide thickness.
15. The memory of claim 14 , wherein the first gate oxide thickness is less than 14 angstroms and wherein the second gate oxide thickness is less than 19 angstroms.