Low voltage memory device and method thereof
View Patent ↗A device is disclosed having a low-voltage memory device. The device includes a first memory having a first memory topology and a second memory having a second memory topology, with both memories located in an integrated circuit. The first memory is a relatively high-density memory device, capable of storing large amounts of data relative to the second memory. The second memory is a low-voltage memory device capable of being accessed at low-voltages relative to the voltage at which the first memory can be accessed. Accordingly, the second memory is accessible when the integrated circuit is placed in a low-voltage mode of operation, which may represent a data retention state (sleep state) for the first memory or other portions of the integrated circuit. Thus, the device is able to store large amounts of data in the high density memory in a normal or active mode of operation, and also have access to the low-voltage memory during the low-voltage mode of operation.
1. A method, comprising:
in a first mode of operation:
providing a first voltage to a first memory having a first minimum operating voltage and to a second memory having a second minimum operating voltage, the second minimum operating voltage being different from the first minimum operating voltage, wherein the first memory and the second memory are located within an integrated circuit;
accessing the first memory;
accessing the second memory; and
in a second mode of operation:
providing a second voltage to the first memory and to the second memory,
wherein the second voltage is less than the first minimum operating voltage;
accessing the second memory to retrieve status data associated with data stored in the first memory from the second memory; and
in response to determining the status data indicates data corresponding to data stored in the first memory has been changed, providing the first voltage to the first memory.
2. The method of claim 1 , further comprising:
receiving a low-voltage mode of operation indication; and
changing a mode of operation for the integrated circuit to the second mode of operation from the first mode of operation in response to the low-voltage mode of operation indication.
3. The method of claim 1 , further comprising:
receiving an active mode of operation indication; and
changing a mode of operation for the integrated circuit to the first mode of operation from the second mode of operation in response to the active mode of operation indication.
4. The method of claim 1 , wherein the first memory has a first memory cell topology and the second memory has a second memory cell topology different from the first memory cell topology, and wherein the second memory cell topology comprises a full pass gate controllable by a write control line.
5. The method of claim 4 , wherein the first memory cell topology comprises a single transistor pass gate.
6. A method, comprising:
in a first mode of operation, accessing a first memory located within an integrated circuit using a first access voltage, the first memory having a first memory topology comprising a first arrangement of transistors;
in a second mode of operation, accessing status data at a second memory located within the integrated circuit using a second access voltage less than the first access voltage, the second memory having a second memory topology comprising a second arrangement of transistors, wherein the first memory is substantially inaccessible to write operations at the second access voltage and wherein the second arrangement of transistors is different than the first arrangement of transistors, the status data indicative of a status of data stored at the first memory; and
providing the first access voltage to the first memory in response to determining the status data indicates data corresponding to the data stored at the first memory has changed.
7. The method of claim 6 , wherein the first memory is substantially inaccessible to read operations at the second access voltage.
8. The method of claim 6 , further comprising:
providing the second access voltage to the first memory; and
retaining data in the first memory when the second access voltage is provided to the first memory.
9. The method of claim 8 , further comprising:
receiving an access request for the first memory when the second access voltage is provided to the first memory; and
providing the first access voltage to the first memory responsive to receiving the access request.
10. The method of claim 6 , further comprising:
receiving a low-voltage mode of operation indication; and
providing the second access voltage to the first memory and the second memory responsive to receiving the low-voltage mode of operation indication.
11. A device, comprising:
a first memory located within an integrated circuit, the first memory having a first memory cell topology with a first minimum operating voltage, the first memory cell topology comprising a first arrangement of transistors;
a second memory located within the integrated circuit, the second memory having a second memory cell topology with a second minimum operating voltage, wherein the second minimum operating voltage is less than the first minimum operating voltage and wherein the second memory cell topology comprises a second arrangement of transistors, the second arrangement of transistors different from the first arrangement of transistors, the second memory configured to store status information indicative of a status of data stored at the first memory; and
a processing core located at the integrated circuit, the processing core operable to:
access the first memory and the second memory when in a first mode of operation, and to access the second memory but not the first memory when in a second mode of operation;
access the status information in the second mode of operation; and
enter the first mode of operation in response to the status information indicating data corresponding to the data stored at the first memory has changed.
12. The device of claim 11 , wherein the first mode of operation comprises an active mode of operation of the integrated circuit.
13. The device of claim 11 , wherein the first memory is coupled to a first power supply terminal and the second memory is coupled to a second power supply terminal different from the first power supply terminal.
14. The device of claim 11 , wherein the first memory and the second memory are each coupled to a common power supply terminal.
15. The device of claim 11 , wherein the first memory cell topology comprises a first static random access memory (SRAM) cell topology and the second memory cell topology comprises a second SRAM cell topology, wherein the first SRAM cell topology comprises fewer transistors than the second SRAM cell topology.
16. The device of claim 11 , wherein the second memory cell topology comprises a full pass gate controllable by a write control line.
17. The device of claim 11 , wherein the first memory stores a set of data and the second memory stores a subset of the set of data.
18. The device of claim 11 , wherein the first memory is operable at a first minimum write voltage and the second memory is operable at a second minimum write voltage, the second minimum write voltage less than the first minimum write voltage.