Patent Assignment
Reel/Frame 042374/0001
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2017-04-29
Received: 2017-04-29
Pages: 25
Assignor
NXP USA, INC.
Executed: 2017-04-12
Assignee
VLSI TECHNOLOGY LLC
1209 ORANGE STREET, WILMINGTON, DE, 19801, UNITED STATES
Covered Applications
(46)
ETCH STOP FOR AIRGAP PROTECTION
App. No. 15/594,757
→
TRANSFORMER SYSTEM
App. No. 15/594,745
→
COSMETIC SPONGE
App. No. 29/602,705
→
MOBILE DEVICE ACTIVITY DETECTION
App. No. 15/468,969
→
MAGNETIC MEMORY DEVICE
App. No. 15/270,672
→
MAGNETORESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME
App. No. 15/261,786
→
LATERAL DISTRACTOR
App. No. 14/994,476
→
Method of Forming Different Voltage Devices with High-K Metal Gate
App. No. 14/843,364
→
APPARATUS AND METHOD FOR PREVENTING MULTIPLE RESETS
App. No. 14/269,194
→
Method of Forming Different Voltage Devices with High-K Metal Gate
App. No. 14/021,485
→
SYSTEM AND METHOD FOR LOW-LATENCY ADDRESSING IN FLASH MEMORY
App. No. 13/925,807
→
DYNAMIC READ SCHEME FOR HIGH RELIABILITY HIGH PERFORMANCE FLASH MEMORY
App. No. 13/679,481
→
INTEGRATED CIRCUIT DEVICE, CALIBRATION MODULE, AND METHOD THEREFOR
App. No. 13/634,726
→
SENSING DEVICE AND RELATED OPERATING METHODS
App. No. 13/523,675
→
STACKED DIE SEMICONDUCTOR PACKAGE
App. No. 13/490,451
→
MRAM DEVICE AND METHOD OF ASSEMBLING SAME
App. No. 13/334,006
→
METHOD FOR SUPPLYING AN OUTPUT SUPPLY VOLTAGE TO A POWER GATED CIRCUIT AND AN INTEGRATED CIRCUIT
App. No. 12/787,457
→
PHASE-LOCKED LOOP HAVING A FEEDBACK CLOCK DETECTOR CIRCUIT AND METHOD THEREFOR
App. No. 12/695,461
→
SYSTEM AND METHOD FOR COMMUNICATING BETWEEN MULTIPLE VOLTAGE TIERS
App. No. 12/621,026
→
SYSTEM HAVING MULTIPLE VOLTAGE TIERS AND METHOD THEREFOR
App. No. 12/621,005
→
REGULATOR HAVING INTERLEAVED LATCHES
App. No. 12/555,227
→
VOLTAGE BOOSTING SYSTEM WITH SLEW RATE CONTROL AND METHOD THEREOF
App. No. 12/537,436
→
MEMORY USING MULTIPLE SUPPLY VOLTAGES
App. No. 12/487,791
→
SEMICONDUCTOR SUBSTRATE AND METHOD OF CONNECTING SEMICONDUCTOR DIE TO SUBSTRATE
App. No. 12/471,409
→
SOFT ERROR AND TRANSIENT ERROR DETECTION DEVICE AND METHODS THEREFOR
App. No. 12/415,338
→
DEVICE AND METHOD FOR CONFIGURING INPUT/OUTPUT PADS
App. No. 12/092,463
→
METHOD AND DEVICE FOR HIGH SPEED TESTING OF AN INTEGRATED CIRCUIT
App. No. 11/914,700
→
TURBINE VANE RESTORATION SYSTEM
App. No. 11/823,767
→
METHOD AND APPARATUS FOR AFFECTING A PORTION OF AN INTEGRATED CIRCUIT
App. No. 11/624,454
→
TURBINE VANE AIRFOIL RECONFIGURATION METHOD
App. No. 11/591,908
→
LOW VOLTAGE MEMORY DEVICE AND METHOD THEREOF
App. No. 11/435,942
→
ARRANGEMENT, PHASE LOCKED LOOP AND METHOD FOR NOISE SHAPING IN A PHASE-LOCKED LOOP
App. No. 10/537,634
→
VOLTAGE CONTROLLED OSCILLATOR HAVING DIGITALLY CONTROLLED PHASE ADJUSTMENT AND METHOD THEREFOR
App. No. 11/251,467
→
PROCESS FOR REPAIRING SULFIDATION DAMAGED TURBINE COMPONENTS
App. No. 11/189,347
→
MEMORY BIT LINE SEGMENT ISOLATION
App. No. 10/912,824
→
TEMPERATURE COMPENSATED ON-CHIP BIAS CIRCUIT FOR LINEAR RF HBT POWER AMPLIFIERS
App. No. 10/857,040
→
DURABLE THERMAL BARRIER COATING HAVING LOW THERMAL CONDUCTIVITY
App. No. 10/835,667
→
Integrated circuit with a transistor over an interconnect layer
App. No. 10/423,589
→
THERMAL BARRIER COATING HAVING LOW THERMAL CONDUCTIVITY
App. No. 10/372,570
→
FLIP-CHIP STRUCTURE AND METHOD FOR HIGH QUALITY INDUCTORS AND TRANSFORMERS
App. No. 10/329,081
→
METHOD AND APPARATUS FOR AFFECTING A PORTION OF AN INTEGRATED CIRCUIT
App. No. 10/157,094
→
METHOD FOR REMOVING COATING MATERIAL FROM A COOLING HOLE OF A GAS TURBINE ENGINE COMPONENT
App. No. 09/973,642
→
DUAL STEERED FREQUENCY SYNTHESIZER
App. No. 09/968,178
→
METHOD OF FORMING A BOND PAD AND STRUCTURE THEREOF
App. No. 09/952,527
→
METHOD FOR ADDING FEATURES TO A DESIGN LAYOUT AND PROCESS FOR DESIGNING A MASK
App. No. 09/906,874
→
ABRADEABLE SEAL SYSTEM
App. No. 09/875,764
→