Soft error and transient error detection device and methods therefor
View Patent ↗A clock signal is received at a clock node of a latch module, and a data signal is received at a data node of the latch module. The data signal including information to be latched at a first latch of the latch module and at a second latch of the latch module. A first representation of the data signal to a first data node of the first latch is delayed relative to a second representation of the data signal to a corresponding first data node of the second latch to obtain a first timing requirement between the data signal and the clock signal relative to the first latch that is substantially different than a second timing requirement. An error signal is generated in response to different data being latched at the first latch than at the second latch.
1. A device comprising:
a data input to receive a data signal;
a clock input to receive a clock signal to latch information based on the data signal;
a first signal path including the data input and a first latch, the first signal path having a first delay between the data input and a first data node for a given transition at the data input; and
a second signal path including the data input and a second latch, the second signal path including a first data node at a same location relative to the second latch as the first data node of the first signal path is located relative to the first latch, the second signal path having a second delay between the data input and the first node of the second signal path for the given transition, the second delay being substantially different that the first delay;
wherein the first signal path further comprises a first pass gate comprising a first current electrode coupled to receive information from the data input, and a second current electrode coupled to provide the information to the first latch, the first pass gate having a third delay between the first current electrode and the second current electrode for the given signal; and
wherein the second signal path further comprises a second pass gate comprising a first current electrode coupled to receive information from the data input, and a second current electrode coupled to provide information to the second latch, the second pass gate having a fourth delay between the first current electrode and the second current electrode for the given signal, the difference between the first delay and the second delay is substantially the same as the difference between the third delay and the fourth delay.
2. The device of claim 1 further comprising a data output coupled to the first latch to provide a latched data value.
3. The device of claim 1 wherein the latched data value is based on the first latch but not the second latch.
4. The device of claim 3 further comprising an error output coupled to the first latch and to the second latch to provide an indicator that the latched data value is to be considered invalid.
5. The device of claim 1 wherein the third delay and the forth delay are determined based on respective electrical characteristics of the first pass gate and the second pass gate.
6. The device of claim 1 wherein timing characteristics of a signal provided at the output of the device is not based on the first delay or the second delay.
7. A method comprising:
receiving a signal transition at a data node of a latch module, the signal transition received at substantially the same time at a first source/drain of a first transistor and at a first source/drain of a second transistor;
providing a first representation of the signal transition to a second source/drain of the first transistor at a first time;
providing a second representation of the signal transition to a second source/drain of the second transistor at a second time;
receiving, at a third time, an initial portion of a clock transition at a gate of the first transistor to latch information at a first storage node of the latch module; and
receiving, at substantially the third time, the initial portion of the clock transition at a gate of the second transistor to latch information at a second storage node of the latch module.
8. The method of claim 7 further comprising indicating an error condition based upon information latched at the first storage node and at the second storage node.
9. The method of claim 7 wherein the first time and the second time are determined based on respective electrical characteristics of the first transistor and the second transistor.
10. The method of claim 7 wherein the first time and the second time are determined based on a respective capacitance at the second source/drain of the first transistor and at the second source/drain of the second transistor.