Method for compensating for variations in data timing
View Patent ↗A method for compensating for variations in timing of data sent to a processor on data bit lines relative to a strobe clock sent to the processor on a strobe clock line that can be used in a dual data rate (DDR) memory identifies discrete minimum and maximum time offset values for test data in selected data bit patterns for the data bit lines. The discrete minimum time offset value is the minimum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock and the discrete maximum time offset value is a maximum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock. The discrete minimum and maximum time offset values identify a valid range when the data bit lines supply data in a steady-state condition for latching into the processor by the strobe clock.
1. A method for compensating for variations in timing of data sent on data bit lines relative to a strobe clock sent on a strobe clock line, wherein the data bit lines and the strobe clock line form a link coupling a memory to a processing circuit and wherein the processing circuit comprises a processor and selectable discrete time delays insertable between the processor and link and wherein the strobe clock and the data are sent concurrently over the link from the memory to the processor, the method comprising:
sending a request for selected data bit patterns to be sent from the memory to the processing circuit on the data bit lines, the request being sent from the processing circuit to the memory;
receiving at the processing circuit a set of strobe clocks and the selected data bit patterns, the set of strobe clocks being sent on the strobe clock line and each strobe clock in the set of strobe clocks is sent concurrently from the memory with one of the selected data bit patterns, wherein the selected data bit patterns comprise two alternately received maximum delay data bit patterns that are a one's complement of each other and are common for all of the data bit lines and two alternately received minimum delay data bit patterns for each one of the data bit lines, the two minimum delay data bit patterns being a one's complement of each other;
identifying a discrete minimum time offset value and a discrete maximum time offset value for test data in the selected data bit patterns for each one of the data bit lines, wherein the discrete minimum time offset value is a minimum timing adjustment required to allow the processor to receive the test data in a steady-state condition during a data valid window of the strobe clock and the discrete maximum time offset value is a maximum timing adjustment required to allow the processor to receive the test data in a steady-state condition during a data valid window of the strobe clock, and wherein the discrete minimum time offset value and discrete maximum time offset value identify a valid range when each one of the data bit lines supply data in a steady-state condition for latching into the processor by the strobe clock;
selecting a discrete mid range offset value for each one of the data bit lines, the discrete mid range offset value being determined from the discrete minimum time offset value and a discrete maximum time offset value; and
aligning the discrete mid range offset value of each of the data bit lines by selective inclusion or removal of at least one of the discrete time delays between the processor and link so that the discrete mid range offset value of each of the data bit lines has a common mid range value.
2. The method for compensating for variations in data timing of claim 1 , further comprising:
adjusting the discrete time delays of the strobe clock line by selective inclusion or removal of at least one of the discrete time delays between the processor and link so that a midpoint value of the data valid window is aligned with the common mid range value.
3. The method for compensating for variations in data timing of claim 1 , wherein the maximum delay bit patterns comprise data bits on all data bit lines having the same logic value.
4. The method for compensating for variations in data timing of claim 3 , wherein for a selected one of the data bit lines the minimum delay bit patterns comprise data bits on all other data bit lines having a logic value opposite to the a logic value on the selected one of the data bit lines.
5. The method for compensating for variations in data timing of claim 1 , wherein the strobe clock has a latching threshold value for latching the data and wherein the identifying step includes:
inserting discrete time delays in the strobe clock line to provide an initial set up delay in the strobe clock line and inserting a plurality of the discrete time delays in the data bit lines to ensure that initially the test data received by the processor is in a non-steady-state condition at the latching threshold value of the strobe clock;
identifying the discrete maximum time offset value by selectively removing the discrete time delays in the data bit lines whilst the maximum delay data bit patterns are sent until the processor receives the test data in a steady-state condition at a commencement of one of the data valid windows; and
identifying the discrete minimum time offset value by further selectively removing the discrete time delays in the data bit lines whilst the minimum delay data bit patterns are sent and whilst the processor continues to receive the test data in a steady-state condition during data valid windows.
6. The method for compensating for variations in data timing of claim 5 , wherein selectively removing and further selectively removing are characterized by decrementing the discrete time delays.
7. The method for compensating for variations in data timing of claim 1 , wherein the strobe clock has a latching threshold value for latching the data and, wherein identifying includes:
Inserting discrete time delays in the data bit lines to provide initial setup delays in each of the data bit lines and inserting a plurality of the discrete time delays in the strobe clock line to ensure that initially the test data received by the processor is in a non steady-state condition at the latching threshold value of the strobe clock;
identifying the discrete maximum time offset value by selectively removing the discrete time delays in the strobe clock line whilst the minimum delay data bit patterns are sent until the processor receives the test data in a steady-state condition at a commencement of one of the data valid windows; and
identifying the discrete minimum time offset value by further selectively removing the discrete time delays in the strobe clock line whilst the maximum delay data bit patterns are sent and whilst the processor continues to receive the test data in a steady-state condition during data valid windows.
8. The method for compensating for variations in data timing of claim 7 , wherein selectively removing and further selectively removing are characterized by decrementing the discrete time delays.
9. The method for compensating for variations in data timing of claim 1 , wherein the strobe clock has a latching threshold value for latching the data and wherein identifying includes:
inserting a plurality of the discrete time delays in the data bit lines to ensure that initially the test data received by the processor is in a non steady-state condition at the latching threshold value of the strobe clock;
identifying the discrete minimum time offset value by selectively adding the discrete time delays in the strobe clock line whilst the maximum delay data bit patterns are sent until the processor receives the test data in a steady-state condition at a commencement of one of the data valid windows; and
identifying the discrete maximum time offset value by further selectively adding the discrete time delays in the strobe clock line whilst the minimum delay data bit patterns are sent and whilst the processor continues to receive the test data in a steady-state condition during data valid windows.
10. The method for compensating for variations in data timing of claim 9 , wherein selectively adding and further selectively adding are characterized by incrementing the discrete time delays.
11. The method for compensating for variations in data timing of claim 1 , wherein the strobe clock has a latching threshold value for latching the data and wherein identifying includes:
inserting a plurality of the discrete time delays in the strobe clock line to ensure that initially the test data received by the processor is in a non steady-state condition at the latching threshold value of the strobe clock;
identifying the discrete minimum time offset value by selectively adding the discrete time delays in the data lines whilst the minimum delay data bit patterns are sent until the processor receives the test data in a steady-state condition at a commencement of one of the data valid windows; and
identifying the discrete maximum time offset value by further selectively adding the discrete time delays in the data lines whilst the maximum delay data bit patterns are sent and whilst the processor continues to receive the test data in a steady-state condition during data valid windows.
12. The method for compensating for variations in data timing of claim 11 , wherein selectively adding and further selectively adding are characterized by incrementing the discrete time delays.
13. The method for compensating for variations in data timing of claim 1 , wherein the aligning the discrete mid-range offset value includes adjusting the discrete time delays of the strobe clock line by selecting one of the data bit lines as a reference data bit line with a reference discrete mid-range offset value and adding or removing the discrete time delays in one or more of the other data bit lines.
14. The method for compensating for variations in data timing of claim 13 , wherein the step of adjusting the discrete time delays of the strobe clock line includes:
identifying a middle range value of a range length of the reference data bit line, the range length being identified by calculating the difference between the discrete minimum time offset value and discrete maximum time offset value thereof; and
selectively adding or removing the discrete timing delays in the strobe clock line that provide delay offset equal to the middle range value.
15. The method for compensating for variations in data timing of claim 1 , wherein the discrete minimum offset value and discrete maximum offset value are identified counting the discrete time delays.
16. The method for compensating for variations in data timing of claim 1 , wherein the adjusting the discrete time delays includes adjusting the discrete time delays of the strobe line to align with the midpoint value of each one of the aligned data bit lines.
17. The method for compensating for variations in data timing of claim 1 , wherein the discrete mid-range value offset is a mid-value of a Valid Range Length, wherein the Valid Range Length is the difference between the discrete maximum time offset value and the discrete minimum time offset value.
18. The method for compensating for variations in data timing of claim 1 , wherein the discrete mid-range value offset is an average value of the discrete minimum time offset value and discrete maximum time offset value.
19. In a system having a link between a memory and a processing circuit formed from data bit lines and a strobe clock line, wherein the processing circuit includes a processor and selectable discrete time delays insertable between the processor and link, a method for compensating for variations in timing of data sent over the data bit lines relative to a strobe clock sent on the strobe clock line, and wherein the strobe clock and the data are sent concurrently over the link from the memory to the processor, the method comprising the steps of:
sending a request for selected data bit patterns to be sent from the memory to the processing circuit on the data bit lines, the request being sent from the processing circuit to the memory;
receiving at the processing circuit a set of strobe clocks and the selected data bit patterns, the set of strobe clocks being sent on the strobe clock line and each strobe clock in the set of strobe clocks is sent concurrently from the memory with one of the selected data bit patterns, wherein the selected data bit patterns comprise two alternately received maximum delay data bit patterns that are a one's complement of each other and are common for all of the data bit lines and two alternately received minimum delay data bit patterns for each one of the data bit lines, the two minimum delay data bit patterns being a one's complement of each other;
identifying a discrete minimum time offset value and a discrete maximum time offset value for test data in the selected data bit patterns for each one of the data bit lines, wherein the discrete minimum time offset value is a minimum timing adjustment required to allow the processor to receive the test data in a steady-state condition during a data valid window of the strobe clock and the discrete maximum time offset value is a maximum timing adjustment required to allow the processor to receive the test data in a steady-state condition during a data valid window of the strobe clock, and wherein the discrete minimum time offset value and discrete maximum time offset value identify a valid range when each one of the data bit lines supply data in a steady-state condition for latching into the processor by the strobe clock;
selecting a discrete mid-range offset value for the valid range of each one of the data bit lines, the discrete mid range offset value being determined from the discrete minimum time offset value and a discrete maximum time offset value; and
aligning the discrete mid range offset value of each of the data bit lines by selective inclusion or removal of at least one of the discrete time delays between the processor and link so that the discrete mid range offset value of each of the data bit lines has a common mid range value.
20. The method of claim 19 , further comprising:
adjusting the discrete time delays of the strobe clock line by selective inclusion or removal of at least one of the discrete time delays between the processor and link so that a midpoint value of the data valid window is aligned with the common mid range value.