Granted Patent B2

US 8,289,773 · App. 12/942,260 · Granted Oct 16, 2012

Abstract

Claims (35)

1. A method for erasing a non-volatile memory, the method comprising:

performing a first pre-erase program step on the non-volatile memory;

determining that the non-volatile memory failed to program correctly during the first pre-erase program step;

performing a first soft program step on the non-volatile memory in response to determining that the non-volatile memory failed to program correctly;

determining that the non-volatile memory soft programmed correctly;

performing a second pre-erase program step on the non-volatile memory in response to determining that the non-volatile memory soft programmed correctly during the first soft program step; and

performing an erase step on the non-volatile memory.

2. The method of claim 1 , wherein performing the first pre-erase program step further comprises determining that performing the first pre-erase program step is a first attempt at performing the first pre-erase program step.

3. The method of claim 1 , wherein determining that the non-volatile memory failed to program correctly further comprises determining that the non-volatile memory failed to program correctly during a first attempt of the first pre-erase program step.

4. The method of claim 1 , wherein performing the first soft program step further comprises setting a bit in a non-volatile memory controller when the first soft program step is successful.

5. The method of claim 1 , wherein performing the first soft programming step further comprises compacting a threshold voltage distribution of the non-volatile memory to a predetermined voltage range.

6. The method of claim 1 , further comprising performing a second soft program step on the non-volatile memory after performing the erase step on the non-volatile memory.

7. The method of claim 1 , wherein performing the first pre-erase program step further comprises applying a programming pulse having a first voltage to a control gate of a memory cell of the non-volatile memory.

8. The method of claim 7 , wherein performing the first soft programming step further comprises applying a soft programming pulse having a second voltage to the control gate of the memory cell, wherein the second voltage is lower than the first voltage.

9. A method for erasing a non-volatile memory, the method comprising:

performing a first pre-erase program step on the non-volatile memory;

determining that the non-volatile memory failed to program correctly during a first attempt of the first pre-erase program step;

performing a first soft program step on the non-volatile memory in response to determining that the non-volatile memory failed to program correctly during the first attempt of the pre-erase program step;

determining that the non-volatile memory soft programmed correctly;

performing a second pre-erase program step on the non-volatile memory in response to determining that the non-volatile memory soft programmed correctly during the first soft program step;

performing an erase step on the non-volatile memory; and

performing a second soft program step on the non-volatile memory after performing the erase step.

10. The method of claim 9 , wherein performing a first soft program step further comprises setting a bit in a non-volatile memory controller when the first soft program step is successful.

11. The method of claim 9 , wherein performing the first pre-erase program step further comprises applying a programming pulse having a first voltage to a control gate of a memory cell of the non-volatile memory.

12. The method of claim 11 , wherein performing the first soft programming step further comprises applying a soft programming pulse having a second voltage to the control gate of the memory cell, wherein the second voltage is lower than the first voltage.

13. The method of claim 9 , wherein the method for erasing the non-volatile memory further comprises erasing a NOR type flash memory.

14. A non-volatile memory comprising:

a plurality of non-volatile memory cells; and

a non-volatile memory controller, coupled to the plurality of non-volatile memory cells, the non-volatile memory controller for controlling an erase operation of the plurality of non-volatile memory cells, the erase operation comprising a first pre-erase program step, a first soft program step, a second pre-erase program step, and an erase step, wherein the first soft program step is performed in response to a failed first pre-erase program step, wherein the second pre-erase program step is performed in response to a successful first soft program step, and wherein the erase step is performed after either a successful first pre-erase program step or a successful second pre-erase program step.

15. The non-volatile memory of claim 14 , wherein the non-volatile memory is characterized as being a NOR type flash memory.

16. The non-volatile memory of claim 14 , wherein the non-volatile memory controller further comprises a bit field for storing an indication of a successful first soft program step.

17. The non-volatile memory of claim 16 , wherein the bit field is a portion of a register file in the non-volatile memory controller.

18. The non-volatile memory of claim 14 , wherein the non-volatile memory controller provides a first voltage to a control gate of each of the plurality of non-volatile memory cells during the first pre-erase program step.

19. The non-volatile memory of claim 18 , wherein the non-volatile memory controller provides a second voltage to the control gate of each of the plurality of non-volatile memory cells during the first soft program step, wherein the second voltage is less than the first voltage.

20. The non-volatile memory of claim 14 , wherein the erase operation of the non-volatile memory further comprises a second soft program step, the second soft program step following the erase step.

Assignments (21)