Granted Patent B2

US 8,878,257 · App. 12/794,591 · Granted Nov 4, 2014

Abstract

Claims (11)

1. An ISFET structure comprising:

a substrate;

a source region and a drain region formed within the substrate and having a channel region provided therebetween;

a gate dielectric layer formed over the channel region;

a floating gate structure formed on the gate dielectric over the channel region, the floating gate structure being electrically coupled to a first conductive structure configured to electrically communicate with a fluid having an ion concentration; and

at least one control gate structure formed at least partially in the substrate and electrically coupled to the floating gate structure, the control gate structure configured to accept a voltage bias and to cause the movement of charge between the floating gate structure and the control gate structure in response to the voltage bias;

wherein the at least one control gate structure comprises a control gate electrode coupled to the substrate via a conductive interconnect, and a capacitor structure formed by the substrate, the floating gate, and an oxide layer provided therebetween.

2. The ISFET structure of claim 1 , wherein the capacitor structure is formed between the floating gate and a well provided within the substrate.

3. The ISFET structure of 1 , wherein the at least one control gate structure includes two control gates, each coupled to a respective capacitor structure formed by the substrate, the floating gate, and an oxide layer provided therebetween.

4. The ISFET structure of claim 1 , further including at least one metal-insulator-metal capacitor coupled between the floating gate structure and the first conductive structure.

5. The ISFET structure of claim 1 , wherein the floating gate structure comprises polysilicon.

Assignments (26)