IP Library Granted Patent US 8,927,311
Granted Patent B2
US 8,927,311 · App. 13/028,930 · Granted Jan 6, 2015

MEMS device having variable gap width and method of manufacture

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Quick Facts
Patent No.
US 8,927,311
App. No.
13/028,930
Granted
Jan 6, 2015
Kind
B2
Abstract

A MEMS device ( 40 ) includes a base structure ( 42 ) and a microstructure ( 44 ) suspended above the structure ( 42 ). The base structure ( 42 ) includes an oxide layer ( 50 ) formed on a substrate ( 48 ), a structural layer ( 54 ) formed on the oxide layer ( 50 ), and an insulating layer ( 56 ) formed over the structural layer ( 54 ). A sacrificial layer ( 112 ) is formed overlying the base structure ( 42 ), and the microstructure ( 44 ) is formed in another structural layer ( 116 ) over the sacrificial layer ( 112 ). Methodology ( 90 ) entails removing the sacrificial layer ( 112 ) and a portion of the oxide layer ( 50 ) to release the microstructure ( 44 ) and to expose a top surface ( 52 ) of the substrate ( 48 ). Following removal, a width ( 86 ) of a gap ( 80 ) produced between the microstructure ( 44 ) and the top surface ( 52 ) is greater than a width ( 88 ) of a gap ( 84 ) produced between the microstructure ( 44 ) and the structural layer ( 54 ).

Claims (34)

1. A method for producing a microelectromechanical systems (MEMS) device comprising:

providing a substrate;

forming a first dielectric layer overlying said substrate;

forming a first structural layer overlying said first dielectric layer, wherein said forming said first structural layer comprises producing a sense plate in said first structural layer;

forming a second dielectric layer over said first structural layer to produce a base structure in which a portion of said first dielectric layer is exposed from both of said first structural layer and said second dielectric layer, wherein said sense plate is laterally displaced away from said portion of said first dielectric layer in said base structure, and said sense plate includes openings extending through said sense plate to expose a second portion of said first dielectric layer;

forming a sacrificial layer overlying said portion of said first dielectric layer and said second dielectric layer of said base structure;

forming a second structural layer overlying said sacrificial layer, wherein said forming said second structural layer comprises forming a proof mass in said second structural layer; and

selectively removing said sacrificial layer and said portion of said first dielectric layer to expose a top surface of said substrate underlying said portion of said first dielectric layer and to release said proof mass such that said proof mass is movable relative to said base structure, wherein said selectively removing operation further comprises removing said second portion of said first dielectric layer underlying said sense plate via said openings.

2. A method as claimed in claim 1 wherein said selectively removing operation comprises producing a first gap between said proof mass and said top surface of said substrate and a second gap between said proof mass and said first structural layer, a first width of said first gap being greater than a second width of said second gap.

3. A method as claimed in claim 2 wherein said top surface of said substrate underlying said microstructure defines a non-sensing region for said MEMS device.

4. A method as claimed in claim 1 wherein said first dielectric layer is an oxide layer and said second dielectric layer is a nitride layer.

5. A method as claimed in claim 1 wherein said substrate is a silicon substrate, and said selectively removing operation exposes said top surface of said silicon substrate underlying said portion of said first dielectric layer.

6. A method for producing a microelectromechanical systems (MEMS) device comprising:

providing a substrate;

forming a first dielectric layer overlying said substrate;

forming a first structural layer overlying said first dielectric layer, wherein said forming said first structural layer comprises patterning said first structural layer to form at least one sense plate having openings extending through said at least one sense plate;

forming a second dielectric layer over said first structural layer to produce a base structure in which a portion of said first dielectric layer is exposed from both of said first structural layer and said second dielectric layer;

forming a sacrificial layer overlying said portion of said first dielectric layer and said second dielectric layer of said base structure;

forming a second structural layer overlying said sacrificial layer, wherein said forming said second structural layer comprises forming a proof mass in said second structural layer; and

selectively removing said sacrificial layer and said portion of said first dielectric layer to expose a top surface of said substrate underlying said portion of said first dielectric layer and to release said proof mass such that said proof masss is movable relative to said base structure, wherein said selectively removing operation comprises etching said portion of said first dielectric layer via said openings.

7. A method as claimed in claim 6 wherein said forming said second dielectric layer comprises patterning said second dielectric layer such that said at least one sense plate having said openings is exposed from said second dielectric layer.

8. A method as claimed in claim 6 wherein said etching operation comprises undercutting said at least one sense plate to partially remove said first dielectric layer underlying said at least one sense plate.

9. A method for producing a microelectromechanical systems (MEMS) device comprising:

forming a first dielectric layer overlying a substrate;

forming a first structural layer overlying said first dielectric layer, wherein a sense plate is produced in said first structural layer and said forming said first structural layer comprises forming openings extending through said sense plate;

forming a second dielectric layer over said first structural layer to produce a base structure in which a portion of said first dielectric layer is exposed from both of said first structural layer and said second dielectric layer, and said sense plate is laterally displaced away from said portion of said first dielectric layer in said base structure;

forming a sacrificial layer overlying said portion of said first dielectric layer and said second dielectric layer of said base structure;

forming a second structural layer overlying said sacrificial layer, said forming said second structural layer including forming a proof mass in said second structural layer; and

selectively removing said sacrificial layer and said portion of said first dielectric layer to expose a top surface of said substrate underlying said portion of said first dielectric layer, said selectively removing operation further removing said sacrificial layer underlying said second structural layer to expose said sense plate and to release said proof mass such that said proof mass is spaced apart from said base structure and said proof mass is movable relative to said base structure, and said selectively removing operation comprising etching a second portion of said first dielectric layer underlying said sense plate via said openings, wherein a first gap is produced between said proof mass and said top surface of said substrate and a second gap is produced between said proof mass and said sense plate, a first width of said first gap being greater than a second width of said second gap.

10. A method as claimed in claim 9 wherein said top surface of said substrate underlying said microstructure defines a non-sensing region for said MEMS device.

11. A method as claimed in claim 9 wherein said etching operation comprises undercutting said at least one sense plate to partially remove said first dielectric layer underlying said at least one sense plate.

12. A method as claimed in claim 9 wherein said forming said second dielectric layer comprises patterning said second dielectric layer such that said sense plate is exposed from said second dielectric layer.

13. A method as claimed in claim 9 wherein said first dielectric layer is an oxide layer and said second dielectric layer is a nitride layer.

14. A method as claimed in claim 9 wherein said substrate is a silicon substrate, and said selectively removing operation exposes said top surface of said silicon substrate underlying said portion of said first dielectric layer.

Assignments (31)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2011
From: MCNEIL, ANDREW C.; LIN, YIZHEN; ZHANG, LISA Z.
To: FREESCALE SEMICONDUCTOR, INC.
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