Semiconductor device and differential amplifier circuit therefor
View Patent ↗A differential amplifier circuit comprising a differential amplifier capacitor and a mismatch error cancellation circuitry, a first pair of capacitors, a second pair of capacitors consisting of switching network. The switching network is arranged to operate in a first configuration wherein the first pair of capacitors is operably coupled to differential inputs of the differential amplifier circuit. The switching network is further arranged to operate in second configuration wherein each capacitor of the first pair of capacitors is operably coupled within a feedback loop between an output and an input of the differential amplifier such that the differential amplifier outputs signals representative of the sampled input voltage signals, and the second pair of capacitors are operably coupled in parallel between the outputs of the differential amplifier such that the second pair of capacitors sample the voltage difference between the outputs.
1. A differential amplifier circuit comprising:
capacitor mismatch error cancellation circuitry;
a differential amplifier operably coupled to the capacitor mismatch error cancellation circuitry, the capacitor mismatch error cancellation circuitry comprising a first pair of capacitors, a second pair of capacitors, and a switching network;
wherein the switching network is arranged to operate in a first configuration wherein the first pair of capacitors is operably coupled to differential inputs of the differential amplifier such that the first pair of capacitors sample input voltage signals present on the differential inputs, and each capacitor of the second pair of capacitors is operably coupled within a feedback loop between an output and an input of the differential amplifier;
wherein the switching network is further arranged to operate in a second configuration wherein each capacitor of the first pair of capacitors is operably coupled within a feedback loop between an output and an input of the differential amplifier such that the differential amplifier is set to output signals representative of the sampled input voltage signals, and the second pair of capacitors is operably coupled in parallel between outputs of the differential amplifier such that the second pair of capacitors sample the voltage difference between the outputs.
2. The differential amplifier circuits of claim 1 wherein, when the switching network is arranged to operate in the first configuration, the first pair of capacitors is connected in parallel between the two differential inputs of the differential amplifier circuit such that each capacitor of the first pair of capacitors stores therein a charge representative of a difference between the voltage signals present at the differential inputs.
3. The differential amplifier circuit of claim 2 wherein, when the switching network is arranged to operate in the second configuration, each capacitor of the first pair of capacitors is operably coupled within the feedback loop between the output and the input of the differential amplifier to output twice the difference between the sampled input voltage signals.
4. The differential amplifier circuit of claim 1 wherein, when the switching network is arranged to operate in the first configuration, the first pair of capacitors is connected between the inputs of the differential amplifier circuit and at least one reference signal applied to the differential amplifier circuit such that each capacitor of the first pair of capacitors stores therein a charge representative of a difference between each input voltage signal present at the differential inputs and at least one of the reference signals.
5. The differential amplifier circuit of claim 4 wherein, when the switching network is arranged to operate in the second configuration, each capacitor of the first pair of capacitors is operably coupled within the feedback loop between the output and the input of the differential amplifier thereby causing the differential amplifier to output a combined difference between each of the voltage signals present at the differential inputs at and one of the reference signals, as sampled when the switching network was previously arranged to operate in the first configuration.
6. The differential amplifier circuit of claim 5 wherein, when the switching network is arranged to operate in the second configuration, each capacitor of the second pair of capacitors is operably coupled in parallel between the outputs of the differential amplifier thereby causing each capacitor of the second pair of capacitors to store a charge representative of a combined difference between each of the voltage signals present at the differential inputs and at least one reference signal, as sampled when the switching network was previously arranged to operate in the first configuration.
7. The differential amplifier circuit of claim 4 wherein the switching network being further arranged to operate in a third configuration wherein each capacitor of the second pair of capacitors is operably coupled within a feedback loop between an output and an input of the differential amplifier such that the differential amplifier outputs signals representative of the voltage signals sampled by the second pair of capacitors.
8. The differential amplifier circuit of claim 7 wherein, when the switching network is arranged to operate in the third configuration, each capacitor of the second pair of capacitors is operably coupled within the feedback loop between the output and the input of the differential amplifier thereby causing the differential amplifier to output twice a combined difference between each of the voltage signals present at the differential inputs and at least one reference signal, as sampled when the switching network was previously arranged to operate in the first configuration.
9. The differential amplifier circuit according to claim 1 wherein the differential amplifier comprising an Operational Transconductance Amplifier (OTA).
10. The differential amplifier circuit according to claim 1 wherein the switching network comprising a plurality of switches, at least some of which comprise boot strapped switches.
11. The differential amplifier circuit according to claim 1 wherein the differential amplifier circuit forming a part of a comparator within a cyclic analogue to digital converter.
12. An analogue-to-digital converter comprising:
a differential amplifier circuit comprising capacitor mismatch error cancellation circuitry and a differential amplifier operably coupled to the capacitor mismatch error cancellation circuitry, the capacitor mismatch error cancellation circuitry comprising a first pair of capacitors, a second pair of capacitors and a switching network;
wherein the switching network is arranged to operate a first configuration wherein the first pair of capacitors is operably coupled to differential inputs of the differential amplifier circuit such that the first pair of capacitors sample input voltage signals present on the differential inputs, and each capacitor of the second pair of capacitors is operably coupled within a feedback loop between an output and an input of the differential amplifier; and
wherein the switching network is further arranged to operate in a second configuration wherein each capacitor of the first pair of capacitors is operably coupled within a feedback loop between an output and an input of the differential amplifier such that the differential amplifier is set to output signals representative of the sampled input voltage signals, and the second pair of capacitors is operably coupled in parallel between outputs of the differential amplifier such that the second pair of capacitors sample the voltage difference between the outputs.
13. A semiconductor device comprising a differential amplifier circuit according to claim 1 .
14. The differential amplifier circuit of claim 5 wherein the switching network being further arranged to operate in a third configuration wherein each capacitor of the second pair of capacitors is operably coupled within a feedback loop between an output and an input of the differential amplifier such that the differential amplifier outputs signals representative of the voltage signals sampled by the second pair of capacitors.
15. The differential amplifier circuit of claim 6 wherein the switching network being further arranged to operate in a third configuration wherein each capacitor of the second pair of capacitors is operably coupled within the feedback loop between the output and the input of the differential amplifier such that the differential amplifier outputs signals representative of the voltage signals sampled by the second pair of capacitors.
16. The differential amplifier circuit according to claim 2 wherein the switching network comprising a plurality of switches, at least some of which comprise boot strapped switches.
17. The differential amplifier circuit according to claim 3 wherein the switching network comprising a plurality of switches, at least some of which comprise boot strapped switches.
18. The differential amplifier circuit according to claim 4 wherein the switching network comprising a plurality of switches, at least some of which comprise boot strapped switches.
19. The differential amplifier circuit according to claim 2 wherein the differential amplifier circuit forming a part of a comparator within a cyclic analogue to digital converter.
20. The differential amplifier circuit according to claim 3 wherein the differential amplifier circuit forming a part of a comparator within a cyclic analogue to digital converter.