Memory with low voltage mode operation
View Patent ↗A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method further includes upon transitioning from the normal voltage mode to the low voltage mode, operating the memory cells at a second voltage across each of the memory cells, wherein the second voltage is lower than the first voltage. The method further includes performing an access on a subset of the memory cells while maintaining the second voltage across the memory cells.
1. A method of operating a memory comprising memory cells, the method comprising:
performing a first access on a subset of the memory cells while maintaining a first voltage across the memory cells;
performing a second access on the subset of the memory cells while maintaining a second voltage across the memory cells, the second voltage being less than the first voltage;
wherein during the performing the first access and the second access, the memory receives a first supply voltage at a first voltage supply terminal and a second supply voltage at a second voltage supply terminal, wherein the first voltage is a difference between the first supply voltage and the second supply voltage;
each memory cell of the subset of memory cells is coupled to a bit line of a plurality of bit lines;
wherein for the first access, a voltage swing of the plurality of bit lines is the first voltage;
wherein for the second access, a voltage swing on the plurality of bit lines is the second voltage.
2. The method of claim 1 , wherein the second access is a read.
3. The method of claim 1 , wherein the second access is a write.
4. The method of claim 1 , wherein:
each of the memory cells includes a first voltage supply node and a second voltage supply node, wherein a voltage across a memory cell is a voltage differential between a voltage of the first voltage supply node and a voltage of the second voltage supply node;
the memory includes a voltage regulator circuit coupled to the first voltage supply terminal;
during the first access, the voltage regulator circuit provides the first supply voltage to the first voltage supply nodes of the subset of memory cells;
during the second access, the voltage regulator circuit provides a second supply voltage to the first voltage supply nodes of the subset of the memory cells, the second supply voltage is different from the first supply voltage.
5. The method of claim 4 , wherein:
the first voltage supply terminal is a system ground terminal;
the first supply voltage is system ground;
the second supply voltage is greater than system ground.
6. The method of claim 4 , wherein:
the first voltage supply terminal is a high system supply voltage terminal;
the first supply voltage is a high system supply voltage;
the second supply voltage is less than the high system supply voltage.
7. A method of operating a memory comprising memory cells, the method comprising:
performing a first access on a subset of the memory cells while maintaining a first voltage across the memory cells;
performing a second access on the subset of the memory cells while maintaining a second voltage across the memory cells, the second voltage being less than the first voltage;
wherein during the performing the first access and the second access, the memory receives a first supply voltage at a first voltage supply terminal and a second supply voltage at a second voltage supply terminal, wherein the first voltage is a difference between the first supply voltage and the second supply voltage:
wherein the second access is a read;
performing a write to the subset of memory cells while maintaining the second voltage across the memory cells.
8. A method of operating a memory comprising memory cells, the method comprising:
performing a first access on a subset of the memory cells while maintaining a first voltage across the memory cells;
performing a second access on the subset of the memory cells while maintaining a second voltage across the memory cells, the second voltage being less than the first voltage;
wherein during the performing the first access and the second access, the memory receives a first supply voltage at a first voltage supply terminal and a second supply voltage at a second voltage supply terminal, wherein the first voltage is a difference between the first supply voltage and the second supply voltage:
wherein the second access is a read;
wherein each memory cell of the subset of memory cells is coupled to a bit line of a plurality of bit lines;
wherein the first access is a read;
wherein for the read of the first access, a voltage swing of the plurality of bit lines is the first voltage;
wherein for the read of the second access, a voltage swing of the plurality of bit lines is the second voltage.
9. A method of operating a memory comprising memory cells, the method comprising:
performing a first access on a subset of the memory cells while maintaining a first voltage across the memory cells;
performing a second access on the subset of the memory cells while maintaining a second voltage across the memory cells, the second voltage being less than the first voltage;
wherein during the performing the first access and the second access, the memory receives a first supply voltage at a first voltage supply terminal and a second supply voltage at a second voltage supply terminal, wherein the first voltage is a difference between the first supply voltage and the second supply voltage;
wherein the second access is a write;
wherein each memory cell of the subset of memory cells is coupled to a bit line of a plurality of bit lines;
wherein the first access is a write;
wherein for the write of the first access, a voltage swing of the plurality of bit lines is the first voltage;
wherein for the write of the second access, the voltage swing on the plurality of bit lines is the second voltage.
10. A method of operating a memory comprising memory cells, the method comprising:
performing a first access on a subset of the memory cells while maintaining a first voltage across the memory cells;
performing a second access on the subset of the memory cells while maintaining a second voltage across the memory cells, the second voltage being less than the first voltage;
wherein during the performing the first access and the second access, the memory receives a first supply voltage at a first voltage supply terminal and a second supply voltage at a second voltage supply terminal, wherein the first voltage is a difference between the first supply voltage and the second supply voltage;
wherein the subset of memory cells is coupled to a word line;
wherein during the first access, a voltage difference between an asserted state of the word line and an unasserted state of the word line is the first voltage;
wherein during the second access, a voltage difference between the asserted state of the word line and the unasserted state of the word line is the first voltage.
11. A memory comprising:
a plurality of memory cells, each memory cell of the plurality of memory cells includes a first voltage supply node and a second voltage supply node, wherein a voltage across a memory cell of the plurality of memory cells during an access to the memory cell is a voltage differential between a voltage of the first voltage supply node and a voltage of the second voltage supply node;
a plurality of word lines, each memory cell of the plurality of memory cells is coupled to a word line of the plurality of word lines;
a plurality of bit lines, each memory cell of the plurality of memory cells is coupled to a bit line of the plurality of bit lines;
a first system voltage supply terminal;
a second system voltage supply terminal;
a voltage regulator circuit coupled to the first system voltage supply terminal and the first voltage supply nodes of the memory cells of the plurality of memory cells;
wherein during an access that is characterized as a write access of a memory cell of the plurality of memory cells when in a first mode, the voltage regulator circuit supplies the voltage of the first system voltage supply terminal to the first voltage supply node of the memory cell such that the voltage access the memory cell is a first voltage differential;
wherein during an access that is characterized as a write access of a memory cell of the plurality of memory cells when in a second mode, the voltage regulator circuit supplies a different voltage than the voltage of the first system voltage supply terminal to the first voltage supply node of the memory cell such that the voltage across the memory cell is a second voltage differential that is less than the first voltage differential.
12. The memory of claim 11 , wherein the first system voltage supply terminal is system ground and the first voltage supply nodes are low voltage supply nodes of the memory cells of the plurality of memory cells.
13. The memory of claim 11 , wherein the first system voltage supply terminal is a system high voltage supply terminal and the first voltage supply nodes of the memory cells of the plurality of memory cells are high voltage supply nodes of the memory cells of the plurality of memory cells.
14. The memory of claim 11 , wherein each of the plurality of memory cells is an SRAM memory cell.
15. The memory of claim 11 , wherein each of the plurality of memory cells is an 8 transistor memory cell.
16. The memory of claim 11 , wherein:
during the access to a memory cell of the plurality of memory cells in the first mode, a voltage difference between an asserted state of a word line coupled to the memory cell and an unasserted state of the word line is the first voltage differential;
during the access to a memory cell of the plurality of memory cells in the second mode, a voltage difference between an asserted state of a word line coupled to the memory cell and an unasserted state of the word line is the first voltage differential.
17. The memory of claim 11 , wherein:
during the access to a memory cell of the plurality of memory cells in the first mode, a voltage difference between an asserted state of a word line coupled to the memory cell and an unasserted state of the word line is the first voltage differential;
during the access to a memory cell of the plurality of memory cells in the second mode, a voltage difference between an asserted state of a word line coupled to the memory cell and an unasserted state of the word line is the first voltage differential.
18. A memory comprising:
a plurality of memory cells, each memory cell of the plurality of memory cells includes a first voltage supply node and a second voltage supply node, wherein a voltage across a memory cell of the plurality of memory cells during an access to the memory cell is a voltage differential between a voltage of the first voltage supply node and a voltage of the second voltage supply node;
a plurality of word lines, each memory cell of the plurality of memory cells is coupled to a word line of the plurality of word lines;
a plurality of bit lines, each memory cell of the plurality of memory cells is coupled to a bit line of the plurality of bit lines;
a first system voltage supply terminal;
a second system voltage supply terminal;
a voltage regulator circuit coupled to the first system voltage supply terminal and the first voltage supply nodes of the memory cells of the plurality of memory cells;
wherein during an access of a memory cell of the plurality of memory cells when in a first mode, the voltage regulator circuit supplies the voltage of the first system voltage supply terminal to the first voltage supply node of the memory cell such that the voltage access the memory cell is a first voltage differential;
wherein during an access of a memory cell of the plurality of memory cells when in a second mode, the voltage regulator circuit supplies a different voltage than the voltage of the first system voltage supply terminal to the first voltage supply node of the memory cell such that the voltage across the memory cell is a second voltage differential that is less than the first voltage differential;
during the access to a memory cell of the plurality of memory cells in the first mode, a voltage difference between an asserted state of a word line coupled to the memory cell and an unasserted state of the word line is the first voltage differential;
during the access to a memory cell of the plurality of memory cells in the second mode, a voltage difference between an asserted state of a word line coupled to the memory cell and an unasserted state of the word line is the first voltage differential.
19. A memory comprising:
a plurality of memory cells, each memory cell of the plurality of memory cells includes a first voltage supply node and a second voltage supply node, wherein a voltage across a memory cell of the plurality of memory cells during an access to the memory cell is a voltage differential between a voltage of the first voltage supply node and a voltage of the second voltage supply node;
a plurality of word lines, each memory cell of the plurality of memory cells is coupled to a word line of the plurality of word lines;
a plurality of bit lines, each memory cell of the plurality of memory cells is coupled to a bit line of the plurality of bit lines;
a first system voltage supply terminal;
a second system voltage supply terminal;
a voltage regulator circuit coupled to the first system voltage supply terminal and the first voltage supply nodes of the memory cells of the plurality of memory cells;
wherein during an access of a memory cell of the plurality of memory cells when in a first mode, the voltage regulator circuit supplies the voltage of the first system voltage supply terminal to the first voltage supply node of the memory cell such that the voltage access the memory cell is a first voltage differential;
wherein during an access of a memory cell of the plurality of memory cells when in a second mode, the voltage regulator circuit supplies a different voltage than the voltage of the first system voltage supply terminal to the first voltage supply node of the memory cell such that the voltage across the memory cell is a second voltage differential that is less than the first voltage differential;
during the access to a memory cell of the plurality of memory cells in the first mode, a voltage swing of a bit line of the plurality of bit lines coupled to the memory cell is the first voltage differential;
during the access to a memory cell of the plurality of memory cells in the second mode, a voltage swing of a bit line of the plurality of bit lines coupled to the memory cell is the second voltage differential.
20. A method of operating a memory comprising memory cells, wherein the memory is configured to operate in a normal voltage mode and a low voltage mode, wherein each memory cell of the memory cells includes a low voltage supply node, the method comprising:
in the normal voltage mode, supplying the low voltage supply nodes of the memory cells with a system ground supply voltage;
upon transitioning from the normal voltage mode to the low voltage mode, supplying the low voltage supply nodes with a second supply voltage, wherein the second supply voltage is higher than the system ground supply voltage, such that the memory cells are configured to operate with a lower across the memory cell voltage in the low voltage mode than an across the memory cell voltage at which the memory cells are configured to operate in the normal voltage mode; and
performing an access on a subset of the memory cells using the lower across the memory cell voltage:
wherein the memory further includes a plurality of write bit lines each coupled to a bit line driver of a plurality of bit line drivers, each bit line driver of the plurality including a low voltage supply node;
during the normal voltage mode, supplying the system ground supply voltage to the low voltage supply nodes of the plurality of bit line drivers;
during the low voltage mode, supplying the second supply voltage to the low voltage supply nodes of the plurality of bit line drivers.