IP Library Granted Patent US 8,329,543
Granted Patent B2
US 8,329,543 · App. 13/085,230 · Granted Dec 11, 2012

Method for forming a semiconductor device having nanocrystals

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Quick Facts
Patent No.
US 8,329,543
App. No.
13/085,230
Granted
Dec 11, 2012
Kind
B2
Abstract

A method is provided for forming a semiconductor device having nanocrystals. The method includes: providing a substrate; forming a first insulating layer over a surface of the substrate; forming a first plurality of nanocrystals on the first insulating layer; forming a second insulating layer over the first plurality of nanocrystals; implanting a first material into the second insulating layer; and annealing the first material to form a second plurality of nanocrystals in the second insulating layer. The method may be used to provide a charge storage layer for a non-volatile memory having a greater nanocrystal density.

Claims (48)

1. A method for forming a semiconductor device, the method comprising:

providing a substrate;

forming a first insulating layer over a surface of the substrate;

forming a first plurality of nanocrystals on the first insulating layer;

forming a second insulating layer over the first plurality of nanocrystals;

implanting a first material into the second insulating layer; and

annealing the first material to form a second plurality of nanocrystals in the second insulating layer.

2. The method of claim 1 , wherein forming the first plurality of nanocrystals comprises:

depositing a second material on the first insulating layer; and

annealing the second material to form the first plurality of nanocrystals.

3. The method of claim 2 , wherein the second material may include a semiconductor material or a metal.

4. The method of claim 2 , wherein the second material is amorphous silicon.

5. The method of claim 1 , further comprising:

forming a polysilicon layer over the second insulating layer; and

patterning the polysilicon layer to form a gate stack for a non-volatile memory cell.

6. The method of claim 1 , wherein annealing the first material further comprises annealing the first material at a temperature between about 600 and 950 degrees Celsius.

7. The method of claim 1 , wherein the first and second pluralities of nanocrystals together provide a nanocrystal density greater than about 1E12 nanocrystals per square centimeter (cm 2 ).

8. The method of claim 1 , wherein the first plurality of nanocrystals have an average diameter of between about 50 to 150 Angstroms and the second plurality of nanocrystals have an average diameter of between about 30 to 70 Angstroms.

9. The method of claim 1 , wherein the first and second plurality of nanocrystals provide charge storage for a non-volatile memory cell.

10. A method for forming a semiconductor device, the method comprising:

providing a substrate;

forming a first insulating layer over a surface of the substrate;

depositing a first material on the first insulating layer;

annealing the first material to form a first plurality of nanocrystals;

forming a second insulating layer over the first plurality of nanocrystals;

implanting a second material into the second insulating layer; and

annealing the second material to form a second plurality of nanocrystals in the second insulating layer.

11. The method of claim 10 , wherein the steps of depositing the first material and annealing the first material further comprises depositing and annealing the first material a predetermined number of iterations.

12. The method of claim 10 , further comprising:

forming a polysilicon layer over the second insulating layer; and

patterning the polysilicon layer to form a gate stack for a non-volatile memory cell.

13. The method of claim 10 , wherein annealing the first material further comprises annealing the first material at a temperature between about 600 and 950 degrees Celsius, and wherein annealing the second material further comprises annealing the second material at a temperature between about 600 and 950 degrees Celsius.

14. The method of claim 10 , wherein the first and second pluralities of nanocrystals together provide a nanocrystal density greater than about 1E12 nanocrystals per square centimeter (cm 2 ).

15. The method of claim 10 , wherein the first plurality of nanocrystals have an average diameter of between about 50 to 150 Angstroms and the second plurality of nanocrystals have an average diameter of between about 30 to 70 Angstroms.

16. The method of claim 10 , wherein the first and second plurality of nanocrystals provide charge storage for a non-volatile memory cell.

17. A method for forming a semiconductor device, the method comprising:

providing a semiconductor substrate;

forming a first insulating layer over a surface of the substrate;

depositing amorphous silicon on the first insulating layer;

annealing the amorphous silicon to form a first plurality of nanocrystals;

forming a second insulating layer over the first plurality of nanocrystals;

implanting a semiconductor material into the second insulating layer;

annealing the semiconductor material to form a second plurality of nanocrystals in the second insulating layer;

forming a polysilicon layer over the second insulating layer; and

patterning the polysilicon layer to form a gate stack for a non-volatile memory cell.

18. The method of claim 17 , wherein the first plurality of nanocrystals have an average diameter of between about 50 to 150 Angstroms and the second plurality of nanocrystals have an average diameter of between about 30 to 70 Angstroms.

19. The method of claim 17 , wherein the steps of depositing the amorphous silicon and annealing the amorphous silicon further comprises depositing and annealing the amorphous silicon a predetermined number of iterations.

20. The method of claim 17 , wherein the first and second pluralities of nanocrystals together provide a nanocrystal density greater than about 1E12 nanocrystals per square centimeter (cm 2 ).

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0477 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027621/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2011
From: KANG, SUNG-TAEG; YATER, JANE A.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 026156/0152 →