Decoupling capacitors recessed in shallow trench isolation
View Patent ↗A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer below a trench opening, a capacitor dielectric layer and a recessed top capacitor plate that is covered by an STI region and isolated from cross talk by a sidewall dielectric layer.
1. A method for fabricating a capacitor, comprising:
providing a semiconductor substrate structure having a top surface;
forming a trench opening in the semiconductor substrate structure by selectively removing a portion of the semiconductor substrate structure in a first region to define bottom and sidewall surfaces where the bottom surface exposes a semiconductor region in the semiconductor substrate structure which forms a bottom capacitor plate;
forming a first dielectric layer on the bottom and sidewall surfaces in the trench opening;
anisotropically etching the first dielectric layer in the trench opening to remove the first dielectric layer from the bottom of the trench opening while retaining a sidewall surface layer on the sidewall surface of the trench opening;
forming a capacitor dielectric layer on the bottom of the trench opening;
forming a recessed conductive top capacitor plate layer on the capacitor dielectric layer in the trench opening, the recessed conductive top capacitor plate layer having a top surface which is below the top surface of the semiconductor substrate structure; and
forming a dielectric layer in the trench opening to cover the recessed conductive top capacitor plate layer, the dielectric layer having a bottom surface which is below the top surface of the semiconductor substrate structure.
2. The method of claim 1 , where providing the semiconductor substrate structure comprises providing a semiconductor-on-insulator semiconductor substrate structure comprising a first semiconductor layer and a second semiconductor layer located over at least part of the first semiconductor layer, where the first semiconductor layer comprises the semiconductor region which forms the bottom capacitor plate, and where the second semiconductor layer is separated from the first semiconductor layer by an insulator layer.
3. The method of claim 2 , where forming the trench opening comprises selectively etching a trench opening in the second semiconductor layer and the insulator layer to expose the first semiconductor layer.
4. The method of claim 1 , where the sidewall surface layer in the trench opening is at least twice as thick as the capacitor dielectric layer in the trench opening.
5. The method of claim 1 , where forming the recessed conductive top capacitor plate layer comprises:
depositing a conductive layer on at least the capacitor dielectric layer in the trench opening; and
reducing a thickness of the conductive layer in the trench opening to form the recessed conductive top capacitor plate layer having a top surface which is below the top surface of the semiconductor substrate structure.
6. The method of claim 1 , where forming the recessed conductive top capacitor plate layer comprises:
depositing a conductive layer on at least the capacitor dielectric layer in the trench opening; and
anisotropically etching the conductive layer in the trench opening to form sidewall top capacitor plate structures in the trench opening without removing the capacitor dielectric layer.
7. The method of claim 1 , where forming the recessed conductive top capacitor plate layer comprises depositing a metal-based material on the capacitor dielectric layer in the trench opening as a top capacitor plate having a top surface which is below the top surface of the semiconductor substrate structure.
8. The method of claim 1 , where forming the recessed conductive top capacitor plate layer comprises forming a silicided semiconductor material on the capacitor dielectric layer in the trench opening as a top capacitor plate having a top surface which is below the top surface of the semiconductor substrate structure.
9. The method of claim 1 , where forming the dielectric layer comprises:
depositing an insulating material to cover the recessed conductive top capacitor plate layer and fill the trench opening; and
planarizing the insulating material to form an isolation region in the trench opening.
10. A method for fabricating a capacitor, comprising:
providing a semiconductor substrate structure having a top surface;
forming a shallow trench opening in the semiconductor substrate structure by selectively removing a portion of the semiconductor substrate structure in a first region to define bottom and sidewall surfaces of a trench opening where the bottom surface exposes a semiconductor region in the semiconductor substrate structure which forms at least part of a bottom capacitor plate;
forming one or more dielectric layers on bottom and sidewall surfaces of the trench opening by forming a dielectric layer on the bottom and sidewall surfaces in the trench opening, and anisotropically etching the dielectric layer in the trench opening to partially etch the dielectric layer to form an isolation dielectric layer on the sidewall surface of the trench opening that is at least twice as thick as a capacitor dielectric layer on the bottom surface of the trench opening;
forming a recessed conductive layer on the one or more dielectric layers on the bottom surface of the trench opening as a top capacitor plate, where the recessed conductive layer has a top surface which is below the top surface of the semiconductor substrate structure; and
forming a shallow trench isolation layer over the top capacitor plate, the shallow trench isolation layer having a bottom surface which is below the top surface of the semiconductor substrate structure.
11. The method of claim 10 , where forming the recessed conductive layer comprises:
depositing a conductive layer on at least the one or more dielectric layers on the bottom surface of the trench opening; and
reducing the conductive layer in the trench opening to form the top capacitor plate having a top surface that is recessed from the top surface of the semiconductor substrate structure.
12. The method of claim 10 , where forming the recessed conductive layer comprises:
depositing a conductive layer on at least the one or more dielectric layers on the bottom surface of the trench opening; and
anisotropically etching the conductive layer in the trench opening to form sidewall top capacitor plate structures in the trench opening without removing the one or more dielectric layers on the bottom surface of the trench opening.
13. The method of claim 10 , where forming the recessed conductive layer comprises depositing a metal-based material on the one or more dielectric layers on the bottom surface of the trench opening as a top capacitor plate having a top surface which is recessed below the top surface of the semiconductor substrate structure.
14. The method of claim 10 , where forming the conductive layer comprises forming a silicided semiconductor material on the one or more dielectric layers on the bottom surface of the trench opening as a top capacitor plate.
15. The method of claim 10 , where forming the one or more dielectric layers comprises forming a sidewall surface layer that is at least twice as thick as a bottom surface layer in the trench opening.
16. An integrated circuit trench capacitor structure, comprising:
a first capacitor plate located in a doped semiconductor layer to be located below a trench formed in a substrate structure having a top surface;
a capacitor dielectric layer located on the first capacitor plate and in the trench; and
a recessed second capacitor plate located on the capacitor dielectric layer and made from a conductive material in the trench, where the recessed second capacitor plate has a top surface which is located below the top surface of the substrate structure and which is covered with a shallow trench isolation layer having a bottom surface which is below the top surface of the substrate structure and surrounded by an insulation layer formed on sidewall surfaces of the trench that is thicker than the capacitor dielectric layer to provide electrical isolation from adjacent semiconductor material.
17. The integrated circuit trench capacitor structure of claim 16 , where the insulation layer is formed on sidewall surfaces of the trench and is at least twice as thick as the capacitor dielectric layer.
18. The integrated circuit trench capacitor structure of claim 16 , where the recessed second capacitor plate is formed in a trench that separates a first active area in which is formed one or more first transistors from a second active area in which is formed one or more second transistors.