Integrated circuit comprising frequency generation circuitry for controlling a frequency source
View Patent ↗An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.
1. An integrated circuit comprising:
frequency generation circuitry for controlling a frequency source for use in an automotive radar system, the frequency generation circuitry comprising:
a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source;
a fractional-N divider located within a feedback loop of the PLL; and
frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.
2. The integrated circuit of claim wherein
the frequency pattern control logic is operably coupled to the fractional-N divider Sigma Delta modulation circuitry, and arranged to provide the frequency control signal to the Sigma Delta modulation circuitry; and
the Sigma Delta modulation circuitry is being arranged to modulate the frequency control signal and provide a modulated control signal to the fractional-N divider.
3. The integrated circuit of claim 1 wherein the frequency pattern control logic is configured to generate frequency control signals for a range of frequency modulation schemes.
4. The integrated circuit of claim 3 wherein the frequency pattern control logic is configured to generate frequency control signals for at least one of a group of:
a saw tooth frequency pattern;
a triangle frequency pattern;
a stepped frequency pattern; and
a combined triangle and stepped pattern.
5. The integrated circuit of claim 1 wherein the frequency pattern control logic is arranged to generate a frequency control signal based on a frequency pattern scheme comprising at least one of high and low frequency limit values and a frequency ramp slope value.
6. The integrated circuit of claim 1 wherein the frequency pattern control logic is at least partly controlled by way of values stored within at least one register.
7. The integrated circuit of claim 6 wherein the at least one register is programmable by way of a digital interface.
8. The integrated circuit of claim 1 wherein the frequency pattern control logic is at least partly controlled by way of an embedded state machine.
9. The integrated circuit of claim 1 wherein the frequency pattern control logic is at least partly controlled by way of a dedicated up/down pin or bit.
10. The integrated circuit of claim 1 wherein the frequency pattern control logic comprises:
ramp generator logic arranged to generate the frequency control signal, wherein the ramp generator logic comprises accumulator logic arranged to increment or decrement the frequency control signal by a ramp slope value each clock cycle.
11. The integrated circuit of claim 10 wherein the ramp generator logic further comprises:
overflow detection logic arranged to
detect when the frequency control signal reaches, in the case of an increasing frequency control signal, a high frequency limit value, and in the case of a decreasing frequency control signal, a low frequency limit value, and
upon detection of the frequency control signal reaching the high or low frequency limit value, cause the accumulator logic to transition between incrementing and decrementing the frequency control signal.
12. The integrated circuit of claim 1 wherein the frequency generation circuitry comprises a fractional-N PLL comprising at least one characteristic from a group of: a high and wide variable division ratio, a high resolution Sigma Delta modulator, a high bandwidth, wide frequency control, and low phase noise.
13. A method for controlling a frequency source for an automotive radar system, the method comprising:
generating a frequency control signal;
providing the frequency control signal to a fractional-N divider within a feedback loop of a phase locked loop (PLL); and
controlling the frequency source with a control signal generated by the PLL, wherein the frequency control signal is arranged such that the PLL causes the frequency source to output a Frequency Modulated Continuous Wave (FMCW) output signal.
14. The method of claim 13 further comprising:
generating frequency control signals for a range of frequency modulation schemes.
15. An automotive radar system comprising frequency generation circuitry for controlling a frequency source therefor, the control circuitry comprising:
a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source;
a fractional-N divider located within a feedback loop of the PLL; and
frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL causes the frequency source to output a Frequency Modulated Continuous Wave (FMCW) output signal.
16. The automotive radar system of claim 15 , wherein
the frequency pattern control logic is operably coupled to the fractional-N divider via Sigma Delta modulation circuitry, and arranged to provide the frequency control signal to the Sigma Delta modulation circuitry; and
the Sigma Delta modulation circuitry is arranged to modulate the frequency control signal and provide a modulated control signal to the fractional-N divider.
17. The integrated circuit of claim 15 wherein the frequency pattern control logic is configured to generate frequency control signals for a range of frequency modulation schemes.
18. The integrated circuit of claim 15 wherein the frequency pattern control logic is arranged to generate a frequency control signal based on a frequency pattern scheme comprising at least one of high and low frequency limit values and a frequency ramp slope value.
19. The integrated circuit of claim 15 wherein the frequency pattern control logic is at least partly controlled by way of values stored within at least one register.
20. The integrated circuit of claim 15 wherein the frequency pattern control logic comprises:
ramp generator logic arranged to generate the frequency control signal, wherein the ramp generator logic comprises
accumulator logic arranged to increment or decrement the frequency control signal by a ramp slope value each clock cycle.