Layout technique for stress management cells
View Patent ↗An integrated circuit device layout is created based on charge carrier mobility characteristics of the device's non-functional cells. The charge carrier mobility of the non-functional cells can alter behavioral characteristics such as the hold time, setup time, or leakage current of nearby functional logic cells. Accordingly, a layout tool creates the layout for the integrated circuit device by selecting and placing non-functional cells having different mobility so as to selectively alter the characteristics of nearby logic cells.
1. A method of determining a layout of a data processing device, the method comprising:
selecting, by a device design system, a first cell based on a charge carrier mobility of the first cell and a behavioral characteristic of a second cell; and
placing, by the design system, the first cell in a relationship to the second cell of the data processing device, wherein in response to placing the first cell in the relationship with the second cell, the behavioral characteristic of the second cell is improved;
wherein:
placing the first cell further comprises placing a plurality of cells to surround the second cell, the plurality of cells comprising the first cell and a third cell having a common design with the first cell, wherein each of the plurality of cells having a different charge carrier mobility;
the second cell comprises a logic cell; and
the first cell and the third cell do not perform designated logic operations for the data processing device.
2. The method of claim 1 , wherein the behavioral characteristic of the second cell is based on a setup time associated with the second cell.
3. The method of claim 1 , wherein the behavioral characteristic of the second cell is based on a hold time associated with the second cell.
4. The method of claim 1 , wherein the behavioral characteristic of the second cell is based on a leakage current associated with the second cell.
5. The method of claim 1 , wherein the first cell and the third cell are non-functional cell variants.
6. The method of claim 5 , wherein the non-functional cell variants have different densities of polysilicon.
7. The method of claim 5 , wherein the non-functional cell variants have different n-channel widths.
8. The method of claim 5 , wherein the non-functional cell variants have different numbers of contacts.
9. A method, comprising:
selecting, by a device design system, a first non-functional cell from a plurality of non-functional cells based on a plurality of setup times and the plurality of hold times associated with a set of functional cells for an integrated circuit device, and upon a behavioral characteristic of a functional cell; and
placing, by the device design system, the first non-functional cell at a device layout for the integrated circuit device based on the plurality of setup times and the plurality of hold times associated with the set of functional cells, wherein the placement of the first non-functional cell at the device layout is in a relationship to the functional cell such that the behavioral characteristic of the functional cell is improved;
wherein:
placing the first non-functional cell further comprises placing a plurality of non-functional cells to surround the functional cell, the plurality of non-functional cells comprising the first non-functional cell and a third non-functional cell having a common design with the first non-functional cell, wherein each of the plurality of non-functional cells having a different charge carrier mobility;
the functional cell comprises a logic cell; and
the first non-functional cell and the third non-functional cell do not perform designated logic operations for the data processing device.
10. The method of claim 9 , further comprising:
selecting a second non-functional cell from the plurality of non-functional cells based on the plurality of setup times and the plurality of hold times associated with the set of functional cells; and
placing the second non-functional cell at the first device layout based on the plurality of setup times and the plurality of hold times associated with the set of functional cells.
11. The method of claim 10 , wherein the first non-functional cell has a higher mobility than the second non-functional cell.
12. The method of claim 9 , further comprising forming the integrated circuit device based on the device layout.
13. A non-transitory computer readable medium tangibly embodying a set of instructions to manipulate a processor to determine a layout of a data processing device design by:
selecting a first cell based on a charge carrier mobility of the first cell and a behavioral characteristic of the second cell; and
placing the first cell in a relationship to a second cell of the data processing device, wherein in response to placing the first cell in the relationship with the second cell, the behavioral characteristic of the second cell is improved;
wherein:
placing the first cell further comprises placing a plurality of cells to surround the second cell, the plurality of cells comprising the first cell and a third cell having a common design with the first cell, wherein each of the plurality of cells having a different charge carrier mobility;
the second cell comprises a logic cell; and
the first cell and the third cell do not perform designated logic operations for the data processing device.
14. The computer readable medium of claim 13 , wherein the behavioral characteristic of the second cell is based on a setup time associated with the second cell.
15. The computer readable medium of claim 13 , wherein the behavioral characteristic of the second cell is based on a hold time associated with the second cell.