ROM memory device
View Patent ↗A memory device includes a plurality of read only memory cells, a precharge circuit, and a sense amplifier. A read only memory (ROM) cell of the plurality of ROM cells is coupled to a word line and a bit line. The ROM cell comprises a transistor having a first current electrode coupled to receive a reference voltage, a second current electrode selectively coupled to the bit line based on the programmed state of the ROM cell, and a control electrode coupled to the word line. The precharge circuit is coupled to the bit line. The precharge circuit precharges the bit line to a precharge voltage, wherein the precharge voltage is less than the reference voltage. The sense amplifier is coupled to the bit line and to a power supply voltage terminal for receiving a power supply voltage, wherein the reference voltage is less than the power supply voltage.
1. A memory device comprising:
a plurality of read only memory (ROM) cells, a ROM cell of the plurality of ROM cells coupled to a word line and a bit line, the ROM cell comprising a transistor, the transistor having a first current electrode coupled to receive a reference voltage, a second current electrode selectively coupled to the bit line based on a programmed state of the ROM cell, and a control electrode coupled to the word line;
a precharge circuit coupled to the bit line, the precharge circuit for precharging the bit line to a precharge voltage, wherein the precharge voltage is less than the reference voltage; and
a sense amplifier coupled to the bit line, wherein the sense amplifier is coupled to receive a power supply voltage, and wherein the reference voltage is less than the power supply voltage.
2. The memory device of claim 1 , wherein the precharge voltage is equal to a ground potential.
3. The memory device of claim 1 , wherein the ROM cell further comprises a programmable element coupled between the second current electrode and the bit line, wherein the second current electrode is selectively coupled to the bit line based on a programmed state of the programmable element.
4. The memory device of claim 3 , wherein the programmable element is one of either a contact location, via location, or source region location.
5. The memory device of claim 1 , wherein the reference voltage is less than an asserted state voltage of the word line by at least a threshold voltage of the transistor of the ROM cell.
6. The memory device of claim 1 , wherein the sense amplifier comprises:
a precharging transistor having a first current electrode coupled to a power supply voltage terminal for receiving the power supply voltage, a second current electrode coupled to an output of the sense amplifier, and a control electrode for receiving a control signal; and
a sensing transistor having a first current electrode coupled to the second current electrode of the precharging transistor, a second current electrode coupled to a terminal of the precharge voltage, and a control electrode coupled to the bit line.
7. The memory device of claim 6 , wherein the transistor of the ROM cell has a first threshold voltage and the sensing transistor has a second threshold voltage, and wherein the power supply voltage is greater than or equal to the first threshold voltage plus the second threshold voltage.
8. The memory device of claim 6 , wherein the sensing transistor has a threshold voltage, and wherein the reference voltage is greater than or equal to the threshold voltage.
9. The memory device of claim 1 , wherein the sense amplifier comprises:
a precharging transistor having a first current electrode coupled to a power supply voltage terminal for receiving the power supply voltage, a second current electrode coupled to an output of the sense amplifier, and a control electrode for receiving a control signal, wherein the precharging transistor is for precharging the output of the sense amplifier to the power supply voltage.
10. A memory device comprising:
a plurality of read only memory (ROM) cells, a ROM cell of the plurality of ROM cells coupled to a word line and a bit line, the ROM cell comprising a transistor and a programmable element, the transistor having a drain terminal coupled to a reference voltage terminal for receiving a reference voltage, a source terminal selectively coupled to the bit line based on a programmed state of the programmable element, and a gate terminal coupled to the word line;
a precharge circuit coupled to the bit line, the precharge circuit for precharging the bit line to a precharge voltage in response to a first control signal, wherein the precharge voltage is less than the reference voltage; and
a sense amplifier coupled to the bit line, the sense amplifier comprising:
a first transistor having a first current electrode coupled to a high power supply voltage terminal, a second current electrode coupled to an output terminal of the sense amplifier, and a control electrode coupled to receive a second control signal; and
a second transistor having a first current electrode coupled to the output terminal of the sense amplifier, a second current electrode coupled to a low power supply voltage terminal, and a control electrode coupled to the bit line, wherein the reference voltage is less than a high power supply voltage received at the high power supply voltage terminal.
11. The memory device of claim 10 , wherein the transistor of the ROM cell has a first threshold voltage and the second transistor has a second threshold voltage, and wherein an asserted state voltage of the word line is greater than or equal to the first threshold voltage plus the second threshold voltage.
12. The memory device of claim 10 , wherein the second transistor has a threshold voltage, and wherein the reference voltage is greater than or equal to the threshold voltage.
13. The memory device of claim 10 , wherein the programmable element is one of either a contact location, via location, or source region location.
14. The memory device of claim 10 , wherein the precharge voltage is equal to a voltage of the low power supply voltage terminal.
15. The memory device of claim 10 , wherein the output terminal of the sense amplifier is precharged to the high power supply voltage in response to the second control signal.
16. The memory device of claim 10 , wherein the word line has an asserted voltage level equal to the high power supply voltage.
17. The memory device of claim 10 , wherein the reference voltage is less than the high power supply voltage of the word line by at least a threshold voltage of the transistor of the ROM cell.
18. A method for reading a read only memory (ROM) device, the method comprising:
supplying a sense amplifier with a power supply voltage, the sense amplifier coupled to a bit line;
supplying a plurality of memory cells of the ROM device with a reference voltage, the reference voltage being less than the power supply voltage;
precharging the bit line to a precharge voltage, the precharge voltage being less than the reference voltage;
providing an asserted word line voltage on a selected word line; and
sensing a voltage on the bit line with the sense amplifiers;
wherein the sense amplifier includes a precharging transistor having a first current electrode coupled to a power supply voltage terminal for receiving the power supply voltage, the supplying the sense amplifier with a power supply voltage includes supplying the power supply voltage via the first current electrode, the precharging transistor having a second current electrode coupled to an output of the sense amplifier and a control electrode for receiving a control signal, wherein the precharging transistor is for precharging the output of the sense amplifier to the power supply voltage, the method further comprising asserting the control signal to precharge the output of the sense amplifier to the power supply voltage.
19. The method of claim 18 , wherein precharging the bit line to the precharge voltage further comprises precharging the bit line to ground potential.